公开(公告)号：US11515418B2

公开(公告)日：2022-11-29

申请号：US16886193

申请日：2020-05-28

申请人： STMICROELECTRONICS, INC.

发明人： Qing Liu ,  John H. Zhang

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/267 ,  H01L29/737 ,  H01L27/092 ,  H01L29/739 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238

摘要： A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

公开(公告)号：US11495676B2

公开(公告)日：2022-11-08

申请号：US16988206

申请日：2020-08-07

申请人： STMICROELECTRONICS, INC.

发明人： John H. Zhang

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12

摘要： Stress is introduced into the channel of an SOI FinFET device by transfer directly from a metal gate. In SOI devices in particular, stress transfer efficiency from the metal gate to the channel is nearly 100%. Either tensile or compressive stress can be applied to the fin channel by choosing different materials to be used in the gate stack as the bulk gate material, a gate liner, or a work function material, or by varying processing parameters during deposition of the gate or work function materials. P-gates and N-gates are therefore formed separately. Gate materials suitable for use as stressors include tungsten (W) for NFETs and titanium nitride (TiN) for PFETs. An optical planarization material assists in patterning the stress-inducing metal gates. A simplified process flow is disclosed in which isolation regions are formed without need for a separate mask layer, and gate sidewall spacers are not used.

公开(公告)号：US11482608B2

公开(公告)日：2022-10-25

申请号：US17119867

申请日：2020-12-11

申请人： STMICROELECTRONICS, INC.

发明人： John H. Zhang

IPC分类号： H01L21/8238 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/45 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/285 ,  H01L21/768 ,  C23C14/04 ,  C23C14/22 ,  H01L29/66

摘要： Energy bands of a thin film containing molecular clusters are tuned by controlling the size and the charge of the clusters during thin film deposition. Using atomic layer deposition, an ionic cluster film is formed in the gate region of a nanometer-scale transistor to adjust the threshold voltage, and a neutral cluster film is formed in the source and drain regions to adjust contact resistance. A work function semiconductor material such as a silver bromide or a lanthanum oxide is deposited so as to include clusters of different sizes such as dimers, trimers, and tetramers, formed from isolated monomers. A type of Atomic Layer Deposition system is used to deposit on semiconductor wafers molecular clusters to form thin film junctions having selected energy gaps. A beam of ions contains different ionic clusters which are then selected for deposition by passing the beam through a filter in which different apertures select clusters based on size and orientation.

公开(公告)号：US11264480B2

公开(公告)日：2022-03-01

申请号：US16025982

申请日：2018-07-02

申请人： STMICROELECTRONICS, INC.

发明人： John H. Zhang

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L29/775 ,  H01L21/66 ,  H01L29/45 ,  H01L29/778 ,  H01L29/41 ,  H01L21/265 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10 ,  H01L29/165

摘要： Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase Vt. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease Vt. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies Vt. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.

公开(公告)号：US10937811B2

公开(公告)日：2021-03-02

申请号：US16412357

申请日：2019-05-14

申请人： STMICROELECTRONICS, INC.

发明人： John H. Zhang

IPC分类号： H01L27/12 ,  H01L21/266 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78 ,  H01L27/11 ,  H01L27/092 ,  H01L29/161 ,  H01L21/84 ,  H01L29/66 ,  H01L23/528 ,  H01L27/112

摘要： Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

公开(公告)号：US10861984B2

公开(公告)日：2020-12-08

申请号：US16564860

申请日：2019-09-09

申请人： STMicroelectronics, Inc.

发明人： Qing Liu ,  John H. Zhang

IPC分类号： H01L29/84 ,  H01H59/00 ,  H01H1/00 ,  B82B3/00 ,  H01H49/00 ,  H01L21/02 ,  H01L21/306 ,  H01H50/00

摘要： An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.

公开(公告)号：US10804377B2

公开(公告)日：2020-10-13

申请号：US15920384

申请日：2018-03-13

申请人： STMICROELECTRONICS, INC.

发明人： John H. Zhang

IPC分类号： H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12

摘要： Stress is introduced into the channel of an SOI FinFET device by transfer directly from a metal gate. In SOI devices in particular, stress transfer efficiency from the metal gate to the channel is nearly 100%. Either tensile or compressive stress can be applied to the fin channel by choosing different materials to be used in the gate stack as the bulk gate material, a gate liner, or a work function material, or by varying processing parameters during deposition of the gate or work function materials. P-gates and N-gates are therefore formed separately. Gate materials suitable for use as stressors include tungsten (W) for NFETs and titanium nitride (TiN) for PFETs. An optical planarization material assists in patterning the stress-inducing metal gates. A simplified process flow is disclosed in which isolation regions are formed without need for a separate mask layer, and gate sidewall spacers are not used.

公开(公告)号：US10325927B2

公开(公告)日：2019-06-18

申请号：US15586195

申请日：2017-05-03

申请人： STMICROELECTRONICS, INC.

发明人： John H. Zhang

IPC分类号： H01L27/12 ,  H01L27/092 ,  H01L29/66 ,  H01L27/11 ,  H01L29/161 ,  H01L29/78 ,  H01L23/528 ,  H01L27/112 ,  H01L21/84 ,  H01L21/266 ,  H01L21/8238 ,  H01L29/06

摘要： Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

公开(公告)号：US20190181270A1

公开(公告)日：2019-06-13

申请号：US16228620

申请日：2018-12-20

申请人： STMICROELECTRONICS, INC.

发明人： John H. Zhang

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/12 ,  H01L29/06 ,  H01L29/41 ,  H01L29/775 ,  H01L27/092 ,  H01L29/778 ,  H01L29/417 ,  H01L29/40

摘要： Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.

公开(公告)号：US10319630B2

公开(公告)日：2019-06-11

申请号：US13629411

申请日：2012-09-27

申请人： STMicroelectronics, Inc. ,  International Business Machines Corporation

发明人： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

摘要： A plurality of metal tracks are formed in a plurality of intermetal dielectric layers stacked in an integrated circuit die. Thin protective dielectric layers are formed around the metal tracks. The protective dielectric layers act as a hard mask to define contact vias between metal tracks in the intermetal dielectric layers.