Invention Grant
- Patent Title: Bitcell state retention
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Application No.: US14696050Application Date: 2015-04-24
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Publication No.: US09666257B2Publication Date: 2017-05-30
- Inventor: Charles Augustine , Shigeki Tomishima , James W. Tschanz , Shih-Lien L. Lu
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Konrad Raynes Davda & Victor LLP
- Main IPC: G11C13/00
- IPC: G11C13/00 ; G11C11/16

Abstract:
In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.
Public/Granted literature
- US20160314826A1 BITCELL STATE RETENTION Public/Granted day:2016-10-27
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