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    Distributed and scalable all-digital low dropout integrated voltage regulator
    1.
    发明授权
    Distributed and scalable all-digital low dropout integrated voltage regulator 有权

    公开(公告)号：US11774919B2

    公开(公告)日：2023-10-03

    申请号：US17125768

    申请日：2020-12-17

    Applicant: Intel Corporation

    Inventor： Suyoung Bang ,  Wootaek Lim ,  Eric Samson ,  Charles Augustine ,  Muhammad Khellah

    IPC: G05B11/42 ,  G05B11/12 ,  G05F1/46

    CPC classification number: G05B11/12 ,  G05F1/46

    Abstract: A distributed and scalable all-digital LDO (D-DLDO) voltage regulator allowing rapid scaling across technology nodes. The distributed DLDO includes many tillable DLDO units regulating a single supply voltage with a shared power distribution network (PDN). The D-DLDO includes an all-digital proportional-integral-derivative (PID) controller that receives a first code indicative of a voltage behavior on a power supply rail. A droop detector is provided to compare the first code with a threshold to determine a droop event, wherein information about the droop event is provided to the PID controller, wherein the PID controller generates a second code according to the first code and the information about the droop event. The DLDO includes a plurality of power gates that receive the second code.

    ALL-DIGITAL VOLTAGE MONITOR (ADVM) WITH SINGLE-CYCLE LATENCY
    3.
    发明申请
    ALL-DIGITAL VOLTAGE MONITOR (ADVM) WITH SINGLE-CYCLE LATENCY 有权

    公开(公告)号：US20210242872A1

    公开(公告)日：2021-08-05

    申请号：US17020667

    申请日：2020-09-14

    Applicant: Intel Corporation

    Inventor： Suyoung Bang ,  Eric Samson ,  Wootaek Lim ,  Charles Augustine ,  Muhammad Khellah

    IPC: H03L7/081 ,  G04F10/00 ,  H03L7/085

    Abstract: An all-digital voltage monitor (ADVM) generates a multi-bit output code that changes in proportion to a voltage being monitored, by leveraging the voltage impact on a gate delay. ADVM utilizes a simple delay chain, which receives a clock-cycle-long pulse every clock cycle, such that the monitored supply voltage is sampled for one full cycle every cycle. The outputs of all delay cells of the delay chain collectively represents a current voltage state as a digital thermometer code. In AVDM, a voltage droop event thus results in a decrease in the output code from a nominal value, while an overshoot results in an increase in the output code.

    Bitcell state retention
    4.
    发明授权
    Bitcell state retention 有权

    公开(公告)号：US10600462B2

    公开(公告)日：2020-03-24

    申请号：US15495936

    申请日：2017-04-24

    Applicant: INTEL CORPORATION

    Inventor： Charles Augustine ,  Shigeki Tomishima ,  James W. Tschanz ,  Shih-Lien L. Lu

    IPC: G11C11/00 ,  G11C11/16

    Abstract: In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.

    Flip-flop circuit with low-leakage transistors
    5.
    发明授权
    Flip-flop circuit with low-leakage transistors 有权

    公开(公告)号：US10423203B2

    公开(公告)日：2019-09-24

    申请号：US15392559

    申请日：2016-12-28

    Applicant: Intel Corporation

    Inventor： Charles Augustine ,  Rafael Rios ,  Somnath Paul ,  Muhammad M. Khellah

    IPC: G06F1/26 ,  H03K3/012 ,  G06F1/3293 ,  H03K3/356

    Abstract: Embodiments include apparatuses, methods, and systems for a flip-flop circuit with low-leakage transistors. The flip-flop circuit may be coupled to a logic circuit of an integrated circuit to store data for the logic circuit when the logic circuit is in a sleep state. The flip-flop circuit may pass a data signal for the logic circuit along a signal path. A capacitor may be coupled between the signal path and ground to store a value of the data signal when the logic circuit is in the sleep state. A low-leakage transistor, such as an IGZO transistor, may be coupled between the capacitor and the signal path and may selectively turn on when the logic circuit transitions from the active state to the sleep state to store the value of the data signal in the capacitor. Other embodiments may be described and claimed.

    PRE-SYNAPTIC LEARNING USING DELAYED CAUSAL UPDATES
    6.
    发明申请
    PRE-SYNAPTIC LEARNING USING DELAYED CAUSAL UPDATES 审中-公开

    公开(公告)号：US20180107922A1

    公开(公告)日：2018-04-19

    申请号：US15294666

    申请日：2016-10-14

    Applicant: Intel Corporation

    Inventor： Somnath Paul ,  Charles Augustine ,  Muhammad M. Khellah

    IPC: G06N3/08 ,  G06N99/00

    Abstract: A processor or integrated circuit includes a memory to store weight values for a plurality neuromorphic states and a circuitry coupled to the memory. The circuitry is to detect an incoming data signal for a pre-synaptic neuromorphic state and initiate a time window for the pre-synaptic neuromorphic state in response to detecting the incoming data signal. The circuitry is further to, responsive to detecting an end of the time window: retrieve, from the memory, a weight value for a post-synaptic neuromorphic state for which an outgoing data signal is generated during the time window, the post-synaptic neuromorphic state being a fan-out connection of the pre-synaptic neuromorphic state; perform a causal update to the weight value, according to a learning function, to generate an updated weight value; and store the updated weight value back to the memory.

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