Invention Grant
- Patent Title: Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief
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Application No.: US14697352Application Date: 2015-04-27
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Publication No.: US09666500B2Publication Date: 2017-05-30
- Inventor: Yaojian Lin , Pandi C. Marimuthu , Kang Chen , Hin Hwa Goh , Yu Gu , Il Kwon Shim , Rui Huang , Seng Guan Chow , Jianmin Fang , Xia Feng
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L21/56 ; H01L23/498 ; H01L23/538 ; H01L23/00 ; H01L21/768 ; H01L23/528 ; H01L23/522 ; H01L21/31 ; H01L21/78

Abstract:
A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.
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