- Patent Title: Memory cell retention enhancement through erase state modification
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Application No.: US14554383Application Date: 2014-11-26
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Publication No.: US09672909B2Publication Date: 2017-06-06
- Inventor: Jim Walls , Santosh Murali
- Applicant: Microchip Technology Incorporated
- Applicant Address: US AZ Chandler
- Assignee: MICROCHIP TECHNOLOGY INCORPORATED
- Current Assignee: MICROCHIP TECHNOLOGY INCORPORATED
- Current Assignee Address: US AZ Chandler
- Agency: Slayden Grubert Beard PLLC
- Main IPC: G11C13/00
- IPC: G11C13/00 ; G11C7/04

Abstract:
A method of controlling a resistive memory cell is provided. A resistance threshold value is defined for the memory cell, wherein a circuit identifies the cell as erased if a detected resistance of the cell is above the resistance threshold and identifies the cell as programmed if the detected resistance is below the resistance threshold value. A filament is formed across an electrolyte switching region of the cell by applying an electrical charge, wherein the cell having the formed filament has a first resistance. The cell is then erased to an erased state having a second resistance greater than the first resistance. The cell is then programmed to a quasi-erased state having a third resistance between the first and second resistances, and above the resistance threshold value such that the cell is identified by the circuit as erased. The cell may then be maintained in the quasi-erased state.
Public/Granted literature
- US20150310915A1 Memory Cell Retention Enhancement Through Erase State Modification Public/Granted day:2015-10-29
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