公开(公告)号：US10050131B2

公开(公告)日：2018-08-14

申请号：US15375094

申请日：2016-12-11

Applicant: Microchip Technology Incorporated

Inventor： Jack Wong ,  Sajid Kabeer ,  Mel Hymas ,  Santosh Murali ,  Brad Kopp

IPC: H01L29/66 ,  H01L29/788 ,  H01L21/02 ,  H01L29/423 ,  H01L21/28

Abstract: Methods of fabricating a memory cell of a semiconductor device, e.g., an EEPROM cell, having a sidewall oxide are disclosed. A memory cell structure may be formed including a floating gate and an ONO film over the conductive layer. A sidewall oxide may be formed on a side surface of the floating gate by a process including depositing a thin high temperature oxide (HTO) film on the side surface of the conductive layer, and performing a rapid thermal oxidation (RTO) anneal. The thin HTO film may be deposited before or after performing the RTO anneal. The sidewall oxide formation process may provide an improved memory cell as compared with known prior art techniques, e.g., in terms of endurance and data retention.

公开(公告)号：US20170170303A1

公开(公告)日：2017-06-15

申请号：US15375094

申请日：2016-12-11

Applicant: Microchip Technology Incorporated

Inventor： Jack Wong ,  Sajid Kabeer ,  Mel Hymas ,  Santosh Murali ,  Brad Kopp

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/788

CPC classification number: H01L29/66825 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7881

Abstract: Methods of fabricating a memory cell of a semiconductor device, e.g., an EEPROM cell, having a sidewall oxide are disclosed. A memory cell structure may be formed including a floating gate and an ONO film over the conductive layer. A sidewall oxide may be formed on a side surface of the floating gate by a process including depositing a thin high temperature oxide (HTO) film on the side surface of the conductive layer, and performing a rapid thermal oxidation (RTO) anneal. The thin HTO film may be deposited before or after performing the RTO anneal. The sidewall oxide formation process may provide an improved memory cell as compared with known prior art techniques, e.g., in terms of endurance and data retention.

公开(公告)号：US09672909B2

公开(公告)日：2017-06-06

申请号：US14554383

申请日：2014-11-26

Applicant: Microchip Technology Incorporated

Inventor： Jim Walls ,  Santosh Murali

IPC: G11C13/00 ,  G11C7/04

CPC classification number: G11C13/0069 ,  G11C7/04 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0035 ,  G11C13/0097 ,  G11C2013/0083

Abstract: A method of controlling a resistive memory cell is provided. A resistance threshold value is defined for the memory cell, wherein a circuit identifies the cell as erased if a detected resistance of the cell is above the resistance threshold and identifies the cell as programmed if the detected resistance is below the resistance threshold value. A filament is formed across an electrolyte switching region of the cell by applying an electrical charge, wherein the cell having the formed filament has a first resistance. The cell is then erased to an erased state having a second resistance greater than the first resistance. The cell is then programmed to a quasi-erased state having a third resistance between the first and second resistances, and above the resistance threshold value such that the cell is identified by the circuit as erased. The cell may then be maintained in the quasi-erased state.

公开(公告)号：US20150310915A1

公开(公告)日：2015-10-29

申请号：US14554383

申请日：2014-11-26

Applicant: Microchip Technology Incorporated

Inventor： Jim Walls ,  Santosh Murali

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C7/04 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0035 ,  G11C13/0097 ,  G11C2013/0083

Abstract: A method of controlling a resistive memory cell is provided. A resistance threshold value is defined for the memory cell, wherein a circuit identifies the cell as erased if a detected resistance of the cell is above the resistance threshold and identifies the cell as programmed if the detected resistance is below the resistance threshold value. A filament is formed across an electrolyte switching region of the cell by applying an electrical charge, wherein the cell having the formed filament has a first resistance. The cell is then erased to an erased state having a second resistance greater than the first resistance. The cell is then programmed to a quasi-erased state having a third resistance between the first and second resistances, and above the resistance threshold value such that the cell is identified by the circuit as erased. The cell may then be maintained in the quasi-erased state.

Abstract translation: 提供一种控制电阻式存储单元的方法。 对于存储器单元定义电阻阈值，其中如果检测到的电池电阻高于电阻阈值，则电路将电池识别为擦除，并且如果检测到的电阻低于电阻阈值，则识别该电池被编程。 通过施加电荷在电池的电解质开关区域上形成细丝，其中具有形成的细丝的电池具有第一电阻。 然后将单元擦除到具有大于第一电阻的第二电阻的擦除状态。 然后将单元编程为具有在第一和第二电阻之间的第三电阻并且高于电阻阈值的准擦除状态，使得电池被电路识别为擦除。 然后可以将电池保持在准擦除状态。