ORIENTATION OF A ROTOR
    1.
    发明申请

    公开(公告)号:US20230128564A1

    公开(公告)日:2023-04-27

    申请号:US18049189

    申请日:2022-10-24

    IPC分类号: H02P21/18 H02P21/22

    摘要: One or more examples relate, generally, to an orientation of a rotor. Some examples relate to an apparatus. The apparatus may include sample-accumulation logic to generate, over a time duration, a value indicative of inductance at least partially responsive to a probe signal provided to a stator of a motor. The apparatus may also include a probe-current discriminator to generate a further value indicative of an orientation of a rotor of the motor at least partially responsive to the generated value. The apparatus may also include update logic to update a process variable of a control loop at least partially responsive to a state of the further value.

    METAL-INSULATOR-METAL (MIM) CAPACITOR MODULE

    公开(公告)号:US20230082867A1

    公开(公告)日:2023-03-16

    申请号:US17516141

    申请日:2021-11-01

    发明人: Yaojian Leng

    IPC分类号: H01L49/02 H01L23/522

    摘要: A metal-insulator-metal (MIM) capacitor module is provided. The MIM capacitor module includes a bottom electrode base formed in a lower metal layer, a bottom electrode conductively coupled to the bottom electrode base, a planar insulator formed over the bottom electrode, and a top electrode formed in an upper metal layer over the insulator. The bottom electrode includes a cup-shaped bottom electrode component and a bottom electrode fill component formed in an interior opening defined by the cup-shaped bottom electrode component.

    Semiconductor package having exposed redistribution layer features and related methods of packaging and testing

    公开(公告)号:US11600523B2

    公开(公告)日:2023-03-07

    申请号:US15940807

    申请日:2018-03-29

    发明人: ManKit Lam

    摘要: A method of packaging a semiconductor device having a bond pad on a surface thereof includes forming a redistribution material electrically coupled to the bond pad, forming a dielectric material over the redistribution material, and removing a first portion of the dielectric material to expose a first portion of the redistribution material. Semiconductor packages may include a redistribution layer having a first portion adjacent and coupled to a first contact of the package, a second portion exposed by a first opening in a dielectric material, and a redistribution line electrically coupled to a first bond pad, the first portion, and the second portion. Such a package may be tested placing at least one probe needle in contact with at least one terminal of the package, providing a test signal from the probe needle to the package through the terminal, and detecting signals using the needle.

    DETERMINING A STATE OF A PNT-BASED TIMING SIGNAL

    公开(公告)号:US20230051821A1

    公开(公告)日:2023-02-16

    申请号:US17662975

    申请日:2022-05-11

    IPC分类号: G01S19/21 G01S19/05 G01S19/25

    摘要: Some examples disclosed herein include a method. The method may include determining a relationship between a property of a position, navigation, and timing (PNT)-based timing signal and a property of a virtual time source. The method may also include determining a state of the PNT-based timing signal at least partially responsive to the determined relationship. The method may also include one or more of: providing the PNT-based timing signal at least partially responsive to determining that the state of the PNT-based timing signal corresponds to a first state, disregarding the PNT-based timing signal at least partially responsive to determining that the state of the timing signal corresponds to a second state, and providing an indication of the state of the PNT-based timing signal at least partially responsive to determining that the state of the timing signal corresponds to a second state. Related devices, systems and methods are also disclosed.

    Op-Amp with Random Offset Trim across Input Range with Rail-to-Rail Input

    公开(公告)号:US20230032759A1

    公开(公告)日:2023-02-02

    申请号:US17858685

    申请日:2022-07-06

    IPC分类号: H03F3/45

    摘要: An operational amplifier includes a pre-amplifier circuit, a first trim circuit, and a second trim circuit. The pre-amplifier circuit is to include a differential pair and receive an input voltage. The first trim circuit is to produce an offset voltage correction current and provide the offset voltage correction current to the pre-amplifier circuit to correct an offset of the operational amplifier. The second trim circuit is to produce a common mode voltage (VCM) correction current, provide the VCM voltage correction current to the pre-amplifier circuit, and cause the VCM correction current to have a non-zero value to reduce a correction caused by the offset voltage correction current when the input voltage is within a mid voltage input range. The pre-amplifier circuit is to apply the offset correction current and the VCM correction current to output signals of the differential pair.

    SYSTEM FOR MANAGING A VIRTUAL MEETING

    公开(公告)号:US20230021608A1

    公开(公告)日:2023-01-26

    申请号:US17587211

    申请日:2022-01-28

    摘要: A system for managing a virtual meeting (e.g., video conference) includes memory storing a video conference application and at least one processor to execute the video conference application to generate a virtual meeting view for a first attendee including multiple attendee video streams arranged according to a virtual attendee arrangement specifying positions of the attendee video streams relative to each other in the virtual meeting view, receive second attendee audio data associated with a second attendee video stream, identify a particular video stream position specified by the virtual attendee arrangement, determine differential stereo effect data corresponding with the particular video stream position, and apply the differential stereo effect data to the second attendee audio data to provide differential audio signals on different audio channels output to the first attendee to create a stereo sound effect corresponding with the particular video stream position.

    Introduction and Detection of Parity Error in a UART

    公开(公告)号:US20230011127A1

    公开(公告)日:2023-01-12

    申请号:US17825277

    申请日:2022-05-26

    发明人: Avinash Halageri

    IPC分类号: G06F11/10 G06F11/07

    摘要: A UART includes a transmission register, a receive register, a virtual remappable pin, a parity error check circuit to evaluate contents of the receive register for a parity error, and control logic to determine contents of the transmission register. The contents include underlying data and a parity bit based thereupon. The control logic is to route the contents through the first virtual remappable pin to the receive register. The control logic is to, before reception of the entire contents at the receive register, cause modified contents to be provided to the receive register. The modified contents are to cause a parity error. The modified contents are to include different underlying data or a different parity bit than the contents of the transmission register. The control logic is to determine whether the parity error check circuit detected the parity error.

    Trap sub-portions of computer-readable instructions and related systems, methods, and apparatuses

    公开(公告)号:US11537401B2

    公开(公告)日:2022-12-27

    申请号:US17650621

    申请日:2022-02-10

    发明人: Jacob Lunn Lassen

    摘要: Trap sub-portions of computer-readable instructions and related systems, methods, and devices are disclosed. A processing circuit includes a processing core including a program counter to cycle through addresses and a data storage device including computer-readable instructions stored thereon. Sub-portions of the computer-readable correspond to subroutines. Locations of the sub-portions within the data storage device are associated with the addresses. A first sub-portion at a first location within the data storage device is indicated by a first address. First trap sub-portions at first trap locations are indicated by first trap addresses. The first trap addresses are different from the first address by only a single bit. The first trap sub-portions instruct the processing core to execute first trap subroutines to jump to the first address or back to themselves.

    LINK MONITOR FOR A SWITCH HAVING A PCIE-COMPLIANT INTERFACE, AND RELATED SYSTEMS, DEVICES, AND METHODS

    公开(公告)号:US20220400089A1

    公开(公告)日:2022-12-15

    申请号:US17664334

    申请日:2022-05-20

    发明人: Vincent Hache

    IPC分类号: H04L49/00 H04L49/25 H04L49/15

    摘要: Some embodiments relate to a link monitor for a switch having a PCIe-compliant interface. Some embodiments relate to an apparatus including a Peripheral Component Interconnect Express (PCIe)-compliant interface provided at a PCIe domain of a switch. The apparatus may also include a link monitor provided at a switching fabric of the switch that supports the PCIe domain of the switch. The link monitor to observe a factor-changing event of a state of a fabric link and obtain a value at least partially responsive to a weight computation, the weight computation for a factor associated with the factor-changing event. Related devices, systems and methods are also disclosed.