- 专利标题: Semiconductor device and method of making wafer level chip scale package
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申请号: US14449914申请日: 2014-08-01
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公开(公告)号: US09673093B2公开(公告)日: 2017-06-06
- 发明人: Ming-Che Hsieh , Chien Chen Lee , Baw-Ching Perng
- 申请人: STATS ChipPAC, Ltd.
- 申请人地址: SG Singapore
- 专利权人: STATS ChipPAC Pte. Ltd.
- 当前专利权人: STATS ChipPAC Pte. Ltd.
- 当前专利权人地址: SG Singapore
- 代理机构: Patent Law Group: Atkins and Associates, P.C.
- 代理商 Robert D. Atkins
- 主分类号: H01L23/48
- IPC分类号: H01L23/48 ; H01L21/768 ; H01L23/498 ; H01L23/525 ; H01L23/532 ; H01L21/56 ; H01L23/14 ; H01L23/31 ; H01L23/00
摘要:
A semiconductor device has a semiconductor wafer and a first conductive layer formed over the semiconductor wafer as contact pads. A first insulating layer formed over the first conductive layer. A second conductive layer including an interconnect site is formed over the first conductive layer and first insulating layer. The second conductive layer is formed as a redistribution layer. A second insulating layer is formed over the second conductive layer. An opening is formed in the second insulating layer over the interconnect site. The opening extends to the first insulating layer in an area adjacent to the interconnect site. Alternatively, the opening extends partially through the second insulating layer in an area adjacent to the interconnect site. An interconnect structure is formed within the opening over the interconnect site and over a side surface of the second conductive layer. The semiconductor wafer is singulated into individual semiconductor die.
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