Invention Grant
- Patent Title: Methods and apparatus for vertical bit line structures in three-dimensional nonvolatile memory
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Application No.: US15210915Application Date: 2016-07-15
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Publication No.: US09673304B1Publication Date: 2017-06-06
- Inventor: Michiaki Sano , Akira Nakada , Tetsuya Yamada , Manabu Hayashi , Takashi Matsubara , Sung Tae Lee , Akio Nishida
- Applicant: SANDISK TECHNOLOGIES LLC
- Applicant Address: US TX Plano
- Assignee: SanDisk Technologies LLC
- Current Assignee: SanDisk Technologies LLC
- Current Assignee Address: US TX Plano
- Agency: Vierra Magen Marcus LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L27/115 ; H01L29/792 ; H01L29/788 ; H01L27/11582 ; H01L27/11556 ; H01L27/24 ; H01L45/00

Abstract:
A method is provided that includes forming a dielectric material above a substrate, forming a hole in the dielectric material, the hole disposed in a first direction, forming a word line layer above the substrate via the hole, the word line layer disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material on a sidewall of the hole, forming a local bit line in the hole, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line layer.
Information query
IPC分类: