公开(公告)号：US10256272B2

公开(公告)日：2019-04-09

申请号：US15633092

申请日：2017-06-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yusuke Yoshida ,  Akira Nakada

IPC: H01L45/00 ,  H01L27/24 ,  H01L21/8234

Abstract: A three dimensional ReRAM device includes an etch stop dielectric material layer overlying top surfaces of the dielectric rail structures and the dielectric pillar structures. The etch stop dielectric material layer includes openings in areas that overlie semiconductor pillars of the vertical select transistors. An array of metal nitride portions is located within the openings in the etch stop dielectric material layer. The etch stop dielectric material layer protects the underlying dielectric pillar structures during anisotropic etching steps without covering the metal nitride portions.

公开(公告)号：US09673257B1

公开(公告)日：2017-06-06

申请号：US15172483

申请日：2016-06-03

Applicant: SanDisk Technologies LLC

Inventor： Seje Takaki ,  Manabu Hayashi ,  Akira Nakada ,  Ryousuke Itou ,  Takuro Maede ,  Kengo Kajiwara ,  Tetsuya Yamada

IPC: H01L29/78 ,  H01L27/24 ,  H01L29/66 ,  H01L29/51 ,  H01L45/00 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/528 ,  H01L29/786 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C13/00 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L27/249 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/77 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/2454 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/785 ,  H01L29/78642 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

Abstract: A method is provided that includes forming a transistor by forming a first a rail gate disposed in a first direction above a substrate, forming a second rail gate disposed in a second direction above the substrate, the second direction perpendicular to the first direction, and forming a bridge section disposed between the first rail gate and the second rail gate.

公开(公告)号：US10290803B2

公开(公告)日：2019-05-14

申请号：US15367791

申请日：2016-12-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michiaki Sano ,  Zhen Chen ,  Tetsuya Yamada ,  Akira Nakada ,  Yasuke Oda ,  Manabu Hayashi ,  Shigenori Sato

IPC: H01L27/115 ,  H01L27/24 ,  H01L45/00 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11575

Abstract: A wedge-shaped contact region can be employed to provide electrical contacts to multiple electrically conductive layers in a three-dimensional device structure. A cavity including a generally wedge-shaped region and a primary region is formed in a dielectric matrix layer over a support structure. An alternating stack of insulating layers and electrically conductive layers is formed by a series of conformal deposition processes in the cavity and over the dielectric matrix layer. The alternating stack can be planarized employing the top surface of the dielectric matrix layer as a stopping layer. A tip portion of each electrically conductive layer within remaining portions of the alternating stack is laterally offset from the tip of the generally wedge-shaped region by a respective lateral offset distance along a lateral protrusion direction. Contact via structures can be formed on the tip portions of the electrically conductive layers to provide electrical contact.

公开(公告)号：US09673304B1

公开(公告)日：2017-06-06

申请号：US15210915

申请日：2016-07-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michiaki Sano ,  Akira Nakada ,  Tetsuya Yamada ,  Manabu Hayashi ,  Takashi Matsubara ,  Sung Tae Lee ,  Akio Nishida

IPC: H01L29/66 ,  H01L27/115 ,  H01L29/792 ,  H01L29/788 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2454 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

Abstract: A method is provided that includes forming a dielectric material above a substrate, forming a hole in the dielectric material, the hole disposed in a first direction, forming a word line layer above the substrate via the hole, the word line layer disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material on a sidewall of the hole, forming a local bit line in the hole, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line layer.