A non-volatile memory device includes a memory array having memory cells arranged in wordlines and receiving a supply voltage. A row decoder includes an input and pre-decoding module, which is configured to receive address signals and generate pre-decoded address signals at low voltage, in the range of the supply voltage. A driving module is configured to generate biasing signals for biasing the wordlines of the memory array starting from decoded address signals, which are a function of the pre-decoded address signals, at high voltage and in the range of a boosted voltage higher than the supply voltage. A processing module is configured to receive the pre-decoded address signals and to jointly execute an operation of logic combination and an operation of voltage boosting of the pre-decoded address signals for generation of the decoded address signals.