Invention Grant
- Patent Title: Method for improving transistor performance through reducing the salicide interface resistance
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Application No.: US15220355Application Date: 2016-07-26
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Publication No.: US09680016B2Publication Date: 2017-06-13
- Inventor: Anand Murthy , Boyan Boyanov , Glenn A. Glass , Thomas Hoffmann
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Finch & Maloney PLLC
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/285 ; H01L21/8238 ; H01L29/165 ; H01L29/66 ; H01L29/167 ; H01L29/36 ; H01L29/06 ; H01L29/08 ; H01L29/417

Abstract:
An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
Public/Granted literature
- US20160336447A1 METHOD FOR IMPROVING TRANSISTOR PERFORMANCE THROUGH REDUCING THE SALICIDE INTERFACE RESISTANCE Public/Granted day:2016-11-17
Information query
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