公开(公告)号：US09876113B2

公开(公告)日：2018-01-23

申请号：US15220304

申请日：2016-07-26

Applicant: Intel Corporation

Inventor： Anand Murthy ,  Boyan Boyanov ,  Glenn A. Glass ,  Thomas Hoffmann

IPC: H01L21/78 ,  H01L29/78 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/66 ,  H01L29/167 ,  H01L29/36 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41725 ,  H01L29/6628 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7842 ,  Y10S438/933

Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

公开(公告)号：US09680016B2

公开(公告)日：2017-06-13

申请号：US15220355

申请日：2016-07-26

Applicant: Intel Corporation

Inventor： Anand Murthy ,  Boyan Boyanov ,  Glenn A. Glass ,  Thomas Hoffmann

IPC: H01L29/78 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/66 ,  H01L29/167 ,  H01L29/36 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41725 ,  H01L29/6628 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7842 ,  Y10S438/933

Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.