Invention Grant
- Patent Title: Assist circuit for memory
-
Application No.: US15094755Application Date: 2016-04-08
-
Publication No.: US09685208B2Publication Date: 2017-06-20
- Inventor: Jaydeep P. Kulkarni , Anupama Thaploo , Iqbal Rajwani , Kyung-Hoae Koo , Eric A. Karl , Muhammad Khellah
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C7/12 ; G11C7/22 ; G11C17/16 ; G11C7/10 ; G11C11/419

Abstract:
Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.
Public/Granted literature
- US20160225419A1 ASSIST CIRCUIT FOR MEMORY Public/Granted day:2016-08-04
Information query