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公开(公告)号：US12141890B2
公开(公告)日：2024-11-12
申请号：US17685117
申请日：2022-03-02
Applicant: Intel Corporation
Inventor： Altug Koker , Lance Cheney , Eric Finley , Varghese George , Sanjeev Jahagirdar , Josh Mastronarde , Naveen Matam , Iqbal Rajwani , Lakshminarayanan Striramassarma , Melaku Teshome , Vikranth Vemulapalli , Binoj Xavier
Abstract: A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, cache or DRAM memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.
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公开(公告)号：US11874715B2
公开(公告)日：2024-01-16
申请号：US17966151
申请日：2022-10-14
Applicant: Intel Corporation
Inventor： Nikos Kaburlasos , Iqbal Rajwani , Bhushan Borole , Kamal Sinha , Sanjeev Jahagirdar
IPC: G06F1/00 , G06F1/28 , G06F1/3203 , G06F1/3206
CPC classification number: G06F1/28 , G06F1/3203 , G06F1/3206
Abstract: Dynamic power budget allocation in a multi-processor system is described. In an example, an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.
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公开(公告)号：US20200294181A1
公开(公告)日：2020-09-17
申请号：US16355377
申请日：2019-03-15
Applicant: Intel Corporation
Inventor： Naveen Matam , Lance Cheney , Eric Finley , Varghese George , Sanjeev Jahagirdar , Altug Koker , Josh Mastronarde , Iqbal Rajwani , Lakshminarayanan Striramassarma , Melaku Teshome , Vikranth Vemulapalli , Binoj Xavier
Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.
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公开(公告)号：US09685208B2
公开(公告)日：2017-06-20
申请号：US15094755
申请日：2016-04-08
Applicant: Intel Corporation
Inventor： Jaydeep P. Kulkarni , Anupama Thaploo , Iqbal Rajwani , Kyung-Hoae Koo , Eric A. Karl , Muhammad Khellah
CPC classification number: G11C7/12 , G11C7/1048 , G11C7/1069 , G11C7/22 , G11C11/419 , G11C17/16 , G11C2207/005
Abstract: Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.
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公开(公告)号：US11908542B2
公开(公告)日：2024-02-20
申请号：US16725747
申请日：2019-12-23
Applicant: Intel Corporation
Inventor： Charles Augustine , Somnath Paul , Turbo Majumder , Iqbal Rajwani , Andrew Lines , Altug Koker , Lakshminarayanan Striramassarma , Muhammad Khellah
CPC classification number: G11C7/1048 , G11C7/1006 , G11C7/12 , G11C7/22
Abstract: Prior knowledge of access pattern is leveraged to improve energy dissipation for general matrix operations. This improves memory access energy for a multitude of applications such as image processing, deep neural networks, and scientific computing workloads, for example. In some embodiments, prior knowledge of access pattern allows for burst read and/or write operations. As such, burst mode solution can provide energy savings in both READ (RD) and WRITE (WR) operations. For machine learning or inference, the weight values are known ahead in time (e.g., inference operation), and so the unused bytes in the cache line are exploited to store a sparsity map that is used for disabling read from either upper or lower half of the cache line, thus saving dynamic capacitance.
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Patent Agency Ranking
公开(公告)号：US20230123514A1
公开(公告)日：2023-04-20
申请号：US17504252
申请日：2021-10-18
Applicant: Intel Corporation
Inventor： Gururaj K. Shamanna , Naveen Kumar M. , Jagadeesh Chandra Salaka , Pascal A. Meinerzhagen , Sravan K. Puchakayala , Iqbal Rajwani
IPC: G11C11/419 , H03K3/037 , G11C11/412
Abstract: Embodiments herein relate to optimizing the duration of a sense amp enable signal in a memory device such as SRAM. A control circuit asserts the sense amp enable signal in response to a clock signal from a replica column of the SRAM. A feedback path extends from the sense amps back to the control circuit. In one approach, a change in a feedback signal on the feedback path indicates the sense amps have all received the sense amp enable signal. In another approach, a change in a feedback signal on the feedback path indicates the sense amps have all completed their sensing operations. In some cases, a selection can be made among multiple feedback paths.
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公开(公告)号：US20220180468A1
公开(公告)日：2022-06-09
申请号：US17674781
申请日：2022-02-17
Applicant: Intel Corporation
Inventor： Naveen Matam , Lance Cheney , Eric Finley , Varghese George , Sanjeev Jahagirdar , Altug Koker , Josh Mastronarde , Iqbal Rajwani , Lakshminarayanan Striramassarma , Melaku Teshome , Vikranth Vemulapalli , Binoj Xavier
Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.
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公开(公告)号：US20210133913A1
公开(公告)日：2021-05-06
申请号：US17069188
申请日：2020-10-13
Applicant: Intel Corporation
Inventor： Naveen Matam , Lance Cheney , Eric Finley , Varghese George , Sanjeev Jahagirdar , Altug Koker , Josh Mastronarde , Iqbal Rajwani , Lakshminarayanan Striramassarma , Melaku Teshome , Vikranth Vemulapalli , Binoj Xavier
Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.
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公开(公告)号：US10747286B2
公开(公告)日：2020-08-18
申请号：US16004647
申请日：2018-06-11
Applicant: Intel Corporation
Inventor： Nikos Kaburlasos , Iqbal Rajwani , Bhushan Borole , Kamal Sinha , Sanjeev Jahagirdar
Abstract: Dynamic power budget allocation in a multi-processor system is described. In an example, an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.
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公开(公告)号：US20190377395A1
公开(公告)日：2019-12-12
申请号：US16004647
申请日：2018-06-11
Applicant: Intel Corporation
Inventor： Nikos Kaburlasos , Iqbal Rajwani , Bhushan Borole , Kamal Sinha , Sanjeev Jahagirdar
IPC: G06F1/28
Abstract: Embodiments are generally directed to dynamic power budget allocation in a multi-processor system. An embodiment of an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.
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