Invention Grant
- Patent Title: Integrating VLSI-compatible fin structures with selective epitaxial growth and fabricating devices thereon
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Application No.: US14777736Application Date: 2013-06-28
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Publication No.: US09685381B2Publication Date: 2017-06-20
- Inventor: Niti Goel , Ravi Pillarisetty , Willy Rachmady , Jack T. Kavalieros , Gilbert Dewey , Benjamin Chu-Kung , Marko Radosavljevic , Matthew V. Metz , Niloy Mukherjee , Robert S. Chau
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- International Application: PCT/US2013/048773 WO 20130628
- International Announcement: WO2014/209396 WO 20141231
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L29/267 ; H01L21/02 ; H01L21/762 ; H01L21/8234 ; H01L29/66 ; H01L29/10

Abstract:
Different n- and p-types of device fins are formed by epitaxially growing first epitaxial regions of a first type material from a substrate surface at a bottom of first trenches formed between shallow trench isolation (STI) regions. The STI regions and first trench heights are at least 1.5 times their width. The STI regions are etched away to expose the top surface of the substrate to form second trenches between the first epitaxial regions. A layer of a spacer material is formed in the second trenches on sidewalls of the first epitaxial regions. Second epitaxial regions of a second type material are grown from the substrate surface at a bottom of the second trenches between the first epitaxial regions. Pairs of n- and p-type fins can be formed from the first and second epitaxial regions. The fins are co-integrated and have reduced defects from material interface lattice mismatch.
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