Invention Grant
- Patent Title: Integrated circuit with on-chip power profiling
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Application No.: US14635607Application Date: 2015-03-02
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Publication No.: US09696775B2Publication Date: 2017-07-04
- Inventor: Tian Yan Pu , Chenbo Liu , Thuyen Le , Lars Melzer
- Applicant: INTEL IP CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL IP CORPORATION
- Current Assignee: INTEL IP CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: G06F1/32
- IPC: G06F1/32 ; G06F11/22 ; G06F1/26

Abstract:
Embodiments include apparatuses, methods, and systems for determining a power consumption of a circuit block in an integrated circuit. The integrated circuit may include first and second power supply networks. In some embodiments, the integrated circuit may include a plurality of instances of a circuit block under test. A first instance of the circuit block may be coupled to the first power supply network during a first test run, and a second instance of the circuit block may be coupled to the second power supply network during a second test run. In other embodiments, a single instance of a circuit block under test may be coupled with the first power supply network during a first test run and coupled with the second power supply network during a second test run. The power consumption of the circuit block may be determined based on the first and second test runs.
Public/Granted literature
- US20160259397A1 INTEGRATED CIRCUIT WITH ON-CHIP POWER PROFILING Public/Granted day:2016-09-08
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