Invention Grant
- Patent Title: Method of testing a semiconductor-on-insulator structure and application of said test to the fabrication of such a structure
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Application No.: US14381537Application Date: 2013-02-18
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Publication No.: US09698063B2Publication Date: 2017-07-04
- Inventor: Patrick Reynaud , Walter Schwarzenbach , Konstantin Bourdelle , Jean-Francois Gilbert
- Applicant: Soitec
- Applicant Address: FR Bernin
- Assignee: SOITEC
- Current Assignee: SOITEC
- Current Assignee Address: FR Bernin
- Agency: TraskBritt
- Priority: FR1251991 20120305
- International Application: PCT/IB2013/000216 WO 20130218
- International Announcement: WO2013/132301 WO 20130912
- Main IPC: H01L21/66
- IPC: H01L21/66 ; G01R31/26

Abstract:
The invention concerns a method of testing a semiconductor-on-insulator type structure comprising a support substrate, a dielectric layer having a thickness of less than 50 nm and a semiconductor layer, the structure comprising a bonding interface between the dielectric layer and the support substrate or the semiconductor layer or inside the dielectric layer, characterized in that it comprises measuring the charge to breakdown (QBD) of the dielectric layer and in that information is deduced from the measurement relating to the hydrogen concentration in the layer and/or at the bonding interface. The invention also concerns a method of fabricating a batch of semiconductor-on-insulator type structures including carrying out the test on a sample structure from the batch.
Public/Granted literature
Information query
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