Invention Grant
- Patent Title: Interface apparatus and memory bus system
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Application No.: US14530971Application Date: 2014-11-03
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Publication No.: US09703732B2Publication Date: 2017-07-11
- Inventor: Tomoki Ishii , Takao Yamaguchi , Atsushi Yoshida , Satoru Tokutsu , Nobuyuki Ichiguchi
- Applicant: Panasonic Intellectual Property Management Co., Ltd.
- Applicant Address: JP Osaka
- Assignee: Panasonic Intellectual Property Management Co., Ltd.
- Current Assignee: Panasonic Intellectual Property Management Co., Ltd.
- Current Assignee Address: JP Osaka
- Agency: Renner, Otto, Boisselle & Sklar, LLP.
- Priority: JP2013-029934 20130219
- Main IPC: G06F13/16
- IPC: G06F13/16 ; G06F13/42

Abstract:
An exemplary interface apparatus according to the present disclosure connects together an initiator and a packet exchange type bus network formed on the integrated circuit. In the bus network, if the initiator has submitted request data with a deadline time specified, the initiator receives, by the deadline time, response data to be issued by a node in response to the request data. The interface apparatus includes: a correcting circuit which corrects the deadline time of the request data according to the timing when the request data has been submitted, thereby generating corrected deadline time information; a header generator which generates a packet header that stores the corrected deadline time information; and a packetizing processor which generates a request packet based on the request data and the packet header.
Public/Granted literature
- US20150052283A1 INTERFACE APPARATUS AND MEMORY BUS SYSTEM Public/Granted day:2015-02-19
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