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Patent Agency Ranking
公开(公告)号：US09942174B2
公开(公告)日：2018-04-10
申请号：US14641197
申请日：2015-03-06
Inventor： Atsushi Yoshida , Tomoki Ishii , Satoru Tokutsu , Takao Yamaguchi , Yuuki Soga
IPC: H04L12/861 , H04L12/801 , H04L12/933 , G06F13/16 , G06F21/85
CPC classification number: H04L49/9057 , G06F13/1626 , G06F13/1673 , G06F21/85 , G06F2221/2141 , H04L47/34 , H04L49/102
Abstract: A bus control device (401a) includes a storage (408) that stores a transmission order of data pieces transmitted from a first node (402) to each second node (403); a sorter (413) that receives data pieces transferred from each second node toward the first node and refers to a predefined sorting rule to determine a sorting destination of each data piece; a buffer (409) that stores the sorted data pieces while classifying the sorted data pieces by the second node as a transmission source; and a connection controller (410) that refers to change permission/rejection information indicating whether or not an order is permitted to be changed while the data piece is transferred from each second node to the first node, and transmits data pieces, the order of which is not changed, from the buffer to the first node in the same order as the transmission order stored on the storage.
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公开(公告)号：US09703732B2
公开(公告)日：2017-07-11
申请号：US14530971
申请日：2014-11-03
Inventor： Tomoki Ishii , Takao Yamaguchi , Atsushi Yoshida , Satoru Tokutsu , Nobuyuki Ichiguchi
CPC classification number: G06F13/1621 , G06F13/1657 , G06F13/1689 , G06F13/4282 , G06F2213/0038
Abstract: An exemplary interface apparatus according to the present disclosure connects together an initiator and a packet exchange type bus network formed on the integrated circuit. In the bus network, if the initiator has submitted request data with a deadline time specified, the initiator receives, by the deadline time, response data to be issued by a node in response to the request data. The interface apparatus includes: a correcting circuit which corrects the deadline time of the request data according to the timing when the request data has been submitted, thereby generating corrected deadline time information; a header generator which generates a packet header that stores the corrected deadline time information; and a packetizing processor which generates a request packet based on the request data and the packet header.
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公开(公告)号：US10305825B2
公开(公告)日：2019-05-28
申请号：US15917124
申请日：2018-03-09
Inventor： Atsushi Yoshida , Tomoki Ishii , Satoru Tokutsu , Takao Yamaguchi , Yuuki Soga
IPC: H04L12/861 , H04L12/801 , H04L12/933 , G06F13/16 , G06F21/85
Abstract: A bus control device (401a) includes a storage (408) that stores a transmission order of data pieces transmitted from a first node (402) to each second node (403); a sorter (413) that receives data pieces transferred from each second node toward the first node and refers to a predefined sorting rule to determine a sorting destination of each data piece; a buffer (409) that stores the sorted data pieces while classifying the sorted data pieces by the second node as a transmission source; and a connection controller (410) that refers to change permission/rejection information indicating whether or not an order is permitted to be changed while the data piece is transferred from each second node to the first node, and transmits data pieces, the order of which is not changed, from the buffer to the first node in the same order as the transmission order stored on the storage.
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公开(公告)号：US09798603B2
公开(公告)日：2017-10-24
申请号：US14708403
申请日：2015-05-11
Inventor： Takao Yamaguchi , Atsushi Yoshida , Tomoki Ishii , Satoru Tokutsu
CPC classification number: G06F11/076 , G06F11/0745 , H04L1/0041 , H04L1/0086 , H04L2001/0094
Abstract: A communication device includes: a receiving terminal; a storage device which stores a rule in which a condition regarding a bus system operation environment and an error tolerance scheme are associated with each other, and information regarding a path length; an error processor which determines the error tolerance scheme by utilizing the condition regarding the bus system operation environment and the rule so as to generate error tolerance information corresponding to the received data according to the determined error tolerance scheme; and a sending terminal for sending at least one packet including the error tolerance information and the data to the bus. The operation environment-related condition is a condition for granting an error tolerance for a transmission path of which a bus path length to another communication device, which is a destination of the data, is greater than a predetermined value.
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公开(公告)号：US09961005B2
公开(公告)日：2018-05-01
申请号：US14641223
申请日：2015-03-06
Inventor： Satoru Tokutsu , Tomoki Ishii , Atsushi Yoshida , Takao Yamaguchi , Nobuyuki Ichiguchi
IPC: H04L12/833 , H04L12/40 , H04L12/46 , H04L12/947
CPC classification number: H04L47/2458 , H04L12/4015 , H04L12/4625 , H04L49/252
Abstract: A bus system (100) for a semiconductor circuit transmits data on a networked bus between a first node and at least one second node via a relay device (250) arranged on the bus. The bus system (100) includes a first bus of a low delay and a second bus of a high delay. The first node generates a plurality of packets by attaching, to the data stored in a buffer (202), information specifying a priority of transmission. The relay device (250) converts a priority based on a priority conversion rule, which is determined based on a transmission delay of the high-delay bus, allocates a buffer of a destination relay device to which each packet is to be sent, based on the converted priority, and sends packets in a descending order. The relay device (250) stores packets in a buffer (252) based on the priority.
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