Invention Grant
- Patent Title: Instructions and logic to interrupt and resume paging in a secure enclave page cache
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Application No.: US14318508Application Date: 2014-06-27
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Publication No.: US09703733B2Publication Date: 2017-07-11
- Inventor: Carlos V. Rozas , Ilya Alexandrovich , Gilbert Neiger , Francis X. McKeen , Ittai Anati , Vedvyas Shanbhogue , Shay Gueron
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F13/24 ; G06F12/0806 ; G06F12/08 ; G06F12/0875 ; G06F21/00 ; G06F21/71 ; G06F21/85

Abstract:
Instructions and logic interrupt and resume paging in secure enclaves. Embodiments include instructions, specify page addresses allocated to a secure enclave, the instructions are decoded for execution by a processor. The processor includes an enclave page cache to store secure data in a first cache line and in a last cache line for a page corresponding to the page address. A page state is read from the first or last cache line for the page when an entry in an enclave page cache mapping for the page indicates only a partial page is stored in the enclave page cache. The entry for a partial page may be set, and a new page state may be recorded in the first cache line when writing-back, or in the last cache line when loading the page when the instruction's execution is being interrupted. Thus the writing-back, or loading can be resumed.
Public/Granted literature
- US20150378941A1 INSTRUCTIONS AND LOGIC TO INTERRUPT AND RESUME PAGING IN A SECURE ENCLAVE PAGE CACHE Public/Granted day:2015-12-31
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