Invention Grant
- Patent Title: Semiconductor device and method of forming fine pitch RDL over semiconductor die in fan-out package
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Application No.: US14139614Application Date: 2013-12-23
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Publication No.: US09721922B2Publication Date: 2017-08-01
- Inventor: Pandi C. Marimuthu , Yaojian Lin , Won Kyoung Choi , Il Kwon Shim
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Pte. Ltd.
- Current Assignee: STATS ChipPAC, Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L25/065 ; H01L23/538 ; H01L23/00 ; H01L23/31 ; H01L21/56

Abstract:
A semiconductor device has a first conductive layer including a plurality of conductive traces. The first conductive layer is formed over a substrate. The conductive traces are formed with a narrow pitch. A first semiconductor die and second semiconductor die are disposed over the first conductive layer. A first encapsulant is deposited over the first and second semiconductor die. The substrate is removed. A second encapsulant is deposited over the first encapsulant. A build-up interconnect structure is formed over the first conductive layer and second encapsulant. The build-up interconnect structure includes a second conductive layer. A first passive device is disposed in the first encapsulant. A second passive device is disposed in the second encapsulant. A vertical interconnect unit is disposed in the second encapsulant. A third conductive layer is formed over second encapsulant and electrically connected to the build-up interconnect structure via the vertical interconnect unit.
Public/Granted literature
- US20150179570A1 Semiconductor Device and Method of Forming Fine Pitch RDL Over Semiconductor Die in Fan-Out Package Public/Granted day:2015-06-25
Information query
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