公开(公告)号：US10453785B2

公开(公告)日：2019-10-22

申请号：US14814906

申请日：2015-07-31

Applicant: STATS ChipPAC, Ltd.

Inventor： Il Kwon Shim ,  Pandi C. Marimuthu ,  Won Kyoung Choi ,  Sze Ping Goh ,  Jose A. Caparas

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L23/538

Abstract: A semiconductor device comprises a first semiconductor package including a conductive layer. A substrate including an interconnect structure is disposed over the conductive layer. The interconnect structure of the substrate with the conductive layer of the first semiconductor package are self-aligned. A plurality of openings is formed in the substrate. An adhesive is disposed between the substrate and the first semiconductor package and in the openings of the substrate. A redistribution layer (RDL) is formed over the first semiconductor package opposite the substrate. A pitch of the substrate is different from a pitch of the RDL. The adhesive extends to the interconnect structure of the substrate. A second semiconductor package is disposed over the substrate and the first semiconductor package.

公开(公告)号：US20160043047A1

公开(公告)日：2016-02-11

申请号：US14814906

申请日：2015-07-31

Applicant: STATS ChipPAC, Ltd.

Inventor： Il Kwon Shim ,  Pandi C. Marimuthu ,  Won Kyoung Choi ,  Sze Ping Goh ,  Jose A. Caparas

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/24155 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/014

Abstract: A semiconductor device comprises a first semiconductor package including a conductive layer. A substrate including an interconnect structure is disposed over the conductive layer. The interconnect structure of the substrate with the conductive layer of the first semiconductor package are self-aligned. A plurality of openings is formed in the substrate. An adhesive is disposed between the substrate and the first semiconductor package and in the openings of the substrate. A redistribution layer (RDL) is formed over the first semiconductor package opposite the substrate. A pitch of the substrate is different from a pitch of the RDL. The adhesive extends to the interconnect structure of the substrate. A second semiconductor package is disposed over the substrate and the first semiconductor package.

Abstract translation: 半导体器件包括包括导电层的第一半导体封装。 包括互连结构的衬底设置在导电层上。 具有第一半导体封装的导电层的衬底的互连结构是自对准的。 在基板上形成多个开口。 粘合剂设置在基板和第一半导体封装之间以及基板的开口中。 在与衬底相对的第一半导体封装件上方形成再分配层（RDL）。 衬底的间距与RDL的间距不同。 粘合剂延伸到基底的互连结构。 第二半导体封装设置在衬底和第一半导体封装之上。

公开(公告)号：US20150171024A1

公开(公告)日：2015-06-18

申请号：US14109313

申请日：2013-12-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Won Kyoung Choi ,  Pandi C. Marimuthu

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/562 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012

Abstract: A semiconductor device has a substrate including a base substrate material and a plurality of conductive vias formed partially though the substrate. A plurality of semiconductor die including a base semiconductor material is disposed over the substrate. A ratio of an encapsulant to a quantity of the semiconductor die is determined for providing structural support for the semiconductor die. An encapsulant is deposited over the semiconductor die and substrate. An amount of the encapsulant is selected based on the determined ratio or based on a total amount of the base substrate material and base semiconductor material. Channels are formed in the encapsulant by removing a portion of the encapsulant in a peripheral region of the semiconductor die. Alternatively, a side surface of the semiconductor die is partially exposed with respect to the encapsulant. A portion of the base substrate material is removed to expose the conductive vias.

Abstract translation: 半导体器件具有包括基底材料和部分地通过衬底形成的多个导电通孔的衬底。 包括基底半导体材料的多个半导体管芯设置在基板上。 确定密封剂与半导体管芯的量的比率以提供半导体管芯的结构支撑。 密封剂沉积在半导体管芯和衬底上。 基于确定的比例或基于基底材料和基底半导体材料的总量来选择一定量的密封剂。 通过在半导体管芯的周边区域中去除一部分密封剂而在密封剂中形成通道。 或者，半导体管芯的侧表面相对于密封剂部分地露出。 去除基底衬底材料的一部分以露出导电通孔。

公开(公告)号：US09837336B2

公开(公告)日：2017-12-05

申请号：US14257850

申请日：2014-04-21

Applicant: STATS ChipPAC, Ltd.

Inventor： Won Kyoung Choi ,  Chang Bum Yong ,  Jae Hun Ku

IPC: H01L23/48 ,  H01L23/31 ,  H01L21/683 ,  H01L25/065 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/6836 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/3178 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05578 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16146 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2224/11 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/01023 ,  H01L2224/05664 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01007 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A notch is formed in the semiconductor wafer around each of the conductive vias. The notch around the conductive vias can be formed by wet etching, dry etching, or LDA. A first insulating layer is formed over a surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer. A portion of the first insulating layer is removed to expose the conductive vias. A first conductive layer and second insulating layer can be formed around the conductive vias. A second conductive layer can be formed over the conductive vias. The notch can extend into the second insulating layer.

公开(公告)号：US09527723B2

公开(公告)日：2016-12-27

申请号：US14643074

申请日：2015-03-10

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Won Kyoung Choi ,  Kang Chen ,  Ivan Micallef

IPC: B81B7/00 ,  B81C1/00 ,  H01L21/56 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

CPC classification number: B81B7/007 ,  B81C1/0023 ,  B81C1/00301 ,  B81C1/00904 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/16 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/13091 ,  H01L2924/15 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure.

Abstract translation: 半导体器件具有与第一半导体管芯相邻的第一半导体管芯和模块化互连结构。 密封剂沉积在第一半导体管芯和模块化互连结构上，作为重构面板。 互连结构形成在第一半导体管芯和模块互连结构之上。 第一半导体管芯的有源区域没有互连结构。 第二半导体管芯安装在第一半导体管芯上，第二半导体管芯的有源表面朝向第一半导体管芯的有效表面。 复原的面板在安装第二半导体管芯之前或之后被分割。 第一或第二半导体管芯包括微机电系统（MEMS）。 第二半导体管芯包括密封剂和形成在第二半导体管芯上的互连结构。 或者，第二半导体管芯安装到设置在互连结构上的插入器。

公开(公告)号：US20150259194A1

公开(公告)日：2015-09-17

申请号：US14643074

申请日：2015-03-10

Applicant: STATS ChipPAC, LTD.

Inventor： Yaojian Lin ,  Won Kyoung Choi ,  Kang Chen ,  Ivan Micallef

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81C1/0023 ,  B81C1/00301 ,  B81C1/00904 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/16 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/13091 ,  H01L2924/15 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure.

Abstract translation: 半导体器件具有与第一半导体管芯相邻的第一半导体管芯和模块化互连结构。 密封剂沉积在第一半导体管芯和模块化互连结构上，作为重构面板。 互连结构形成在第一半导体管芯和模块互连结构之上。 第一半导体管芯的有源区域没有互连结构。 第二半导体管芯安装在第一半导体管芯上，第二半导体管芯的有源表面朝向第一半导体管芯的有效表面。 复原的面板在安装第二半导体管芯之前或之后被分割。 第一或第二半导体管芯包括微机电系统（MEMS）。 第二半导体管芯包括密封剂和形成在第二半导体管芯上的互连结构。 或者，第二半导体管芯安装到设置在互连结构上的插入器。

公开(公告)号：US20140264851A1

公开(公告)日：2014-09-18

申请号：US14288589

申请日：2014-05-28

Applicant: STATS ChipPAC, Ltd.

Inventor： Won Kyoung Choi ,  Chang Beom Yong ,  Jae Hun Ku

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/6836 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11002 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14181 ,  H01L2224/16148 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device has a plurality of conductive vias formed through the semiconductor die with a first insulating layer around the conductive vias. A recess is formed in the first insulating layer around the conductive vias by LDA. A portion of the semiconductor wafer is removed by LDA after forming the recess in the first insulating layer so that the conductive vias extend above a surface of the semiconductor wafer. The first insulating layer extends to the surface of the semiconductor wafer or above the surface of the semiconductor wafer. A second insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the second insulating layer is removed by LDA, while leaving a second portion of the second insulating layer over the surface of the semiconductor wafer around the conductive vias. An electroless plated bump is formed over the conductive vias.

Abstract translation: 半导体器件具有通过半导体管芯形成的多个导电通孔，其具有围绕导电通孔的第一绝缘层。 在LDA的导电通孔周围的第一绝缘层中形成凹部。 在第一绝缘层中形成凹陷之后，半导体晶片的一部分被LDA去除，使得导电通孔延伸到半导体晶片的表面之上。 第一绝缘层延伸到半导体晶片的表面或半导体晶片的表面之上。 第二绝缘层形成在半导体晶片的表面和导电通孔上。 第二绝缘层的第一部分被LDA去除，同时在第二绝缘层的第二部分围绕导电通孔留在半导体晶片的表面上。 在导电通孔上形成无电镀凸块。

公开(公告)号：US20140225279A1

公开(公告)日：2014-08-14

申请号：US14257850

申请日：2014-04-21

Applicant: STATS ChipPAC, Ltd.

Inventor： Won Kyoung Choi ,  Chang Bum Yong ,  Jae Hun Ku

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/6836 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/3178 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05578 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16146 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2224/11 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/01023 ,  H01L2224/05664 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01007 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A notch is formed in the semiconductor wafer around each of the conductive vias. The notch around the conductive vias can be formed by wet etching, dry etching, or LDA. A first insulating layer is formed over a surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer. A portion of the first insulating layer is removed to expose the conductive vias. A first conductive layer and second insulating layer can be formed around the conductive vias. A second conductive layer can be formed over the conductive vias. The notch can extend into the second insulating layer.

Abstract translation: 半导体器件具有形成为半导体晶片的多个导电通孔。 去除半导体晶片的一部分，使得导电通孔延伸到半导体晶片的表面之上。 在每个导电通孔周围的半导体晶片中形成切口。 导电通孔周围的凹口可以通过湿蚀刻，干蚀刻或LDA形成。 第一绝缘层形成在半导体晶片和导电通孔的表面上并进入凹口中，以在导电通孔和半导体晶片之间提供应力消除。 去除第一绝缘层的一部分以露出导电通孔。 可以在导电通孔周围形成第一导电层和第二绝缘层。 可以在导电通孔上形成第二导电层。 凹口可以延伸到第二绝缘层中。

公开(公告)号：US09721922B2

公开(公告)日：2017-08-01

申请号：US14139614

申请日：2013-12-23

Applicant: STATS ChipPAC, Ltd.

Inventor： Pandi C. Marimuthu ,  Yaojian Lin ,  Won Kyoung Choi ,  Il Kwon Shim

IPC: H01L29/66 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a first conductive layer including a plurality of conductive traces. The first conductive layer is formed over a substrate. The conductive traces are formed with a narrow pitch. A first semiconductor die and second semiconductor die are disposed over the first conductive layer. A first encapsulant is deposited over the first and second semiconductor die. The substrate is removed. A second encapsulant is deposited over the first encapsulant. A build-up interconnect structure is formed over the first conductive layer and second encapsulant. The build-up interconnect structure includes a second conductive layer. A first passive device is disposed in the first encapsulant. A second passive device is disposed in the second encapsulant. A vertical interconnect unit is disposed in the second encapsulant. A third conductive layer is formed over second encapsulant and electrically connected to the build-up interconnect structure via the vertical interconnect unit.

公开(公告)号：US09105532B2

公开(公告)日：2015-08-11

申请号：US14503698

申请日：2014-10-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Won Kyoung Choi ,  Pandi C. Marimuthu

IPC: H01L23/485 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/11 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11822 ,  H01L2224/11906 ,  H01L2224/13 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die with a first conductive layer formed over the die. A first insulating layer is formed over the die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is constructed by forming a second insulating layer over the first insulating layer with a second opening having a width less than the first opening and depositing a conductive material into the second opening. The interconnect structure can be a conductive pillar or conductive pad. The interconnect structure has a width less than a width of the first opening. The second conductive layer over the first insulating layer outside the first opening is removed while leaving the second conductive layer under the interconnect structure.

Abstract translation: 半导体器件具有半导体管芯，其具有形成在管芯上的第一导电层。 第一绝缘层形成在管芯上方，第一绝缘层中的第一开口布置在第一导电层上。 在第一绝缘层上形成第二导电层，并在第一导电层上形成第一导电层。 通过在第一绝缘层上形成第二绝缘层，其宽度小于第一开口的第二开口并将导电材料沉积到第二开口中来构造互连结构。 互连结构可以是导电柱或导电垫。 互连结构的宽度小于第一开口的宽度。 除去第一开口外部的第一绝缘层上的第二导电层，同时将第二导电层留在互连结构下。