Invention Grant
- Patent Title: Systems, apparatuses, and methods for synchronizing port entry into a low power status
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Application No.: US15158271Application Date: 2016-05-18
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Publication No.: US09753529B2Publication Date: 2017-09-05
- Inventor: Mahesh Wagh , Su Wei Lim
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely Sokoloff Taylor and Zafman LLP
- Main IPC: G08C17/00
- IPC: G08C17/00 ; G06F1/32 ; H04W52/02 ; G06F9/44 ; G06F13/42
Abstract:
Systems, apparatuses, and method for synchronizing port entry into a lowest power state are described. All logic of a port placed into an intermediate state prior to entry into the lowest power state.
Public/Granted literature
- US20160259400A1 SYSTEMS, APPARATUSES, AND METHODS FOR SYNCHRONIZING PORT ENTRY INTO A LOW POWER STATUS Public/Granted day:2016-09-08
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