- Patent Title: Method and circuitry for controlling a depletion-mode transistor
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Application No.: US14542962Application Date: 2014-11-17
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Publication No.: US09762230B2Publication Date: 2017-09-12
- Inventor: Michael Douglas Seeman , Sandeep R. Bahl , David I. Anderson
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Michael A. Davis, Jr.; Charles A. Brill; Frank D. Cimino
- Main IPC: H03K17/082
- IPC: H03K17/082 ; H03K17/08 ; H02H3/00 ; H03K3/012

Abstract:
In described examples, a first transistor has: a drain coupled to a source of a depletion-mode transistor; a source coupled to a first voltage node; and a gate coupled to a control node. A second transistor has: a drain coupled to a gate of the depletion-mode transistor; a source coupled to the first voltage node; and a gate coupled through at least one first logic device to an input node. A third transistor has: a drain coupled to the gate of the depletion-mode transistor; a source coupled to a second voltage node; and a gate coupled through at least one second logic device to the input node.
Public/Granted literature
- US20150137619A1 METHOD AND CIRCUITRY FOR CONTROLLING A DEPLETION-MODE TRANSISTOR Public/Granted day:2015-05-21
Information query
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