公开(公告)号：US20210167767A1

公开(公告)日：2021-06-03

申请号：US17173981

申请日：2021-02-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Douglas Seeman ,  Sandeep R. Bahl ,  David I. Anderson

IPC: H03K17/082 ,  H03K17/08 ,  H03K17/10 ,  H02H3/00 ,  H03K3/012

Abstract: In described examples, a first transistor has: a drain coupled to a source of a depletion-mode transistor; a source coupled to a first voltage node; and a gate coupled to a control node. A second transistor has: a drain coupled to a gate of the depletion-mode transistor; a source coupled to the first voltage node; and a gate coupled through at least one first logic device to an input node. A third transistor has: a drain coupled to the gate of the depletion-mode transistor; a source coupled to a second voltage node; and a gate coupled through at least one second logic device to the input node.

公开(公告)号：US20180006640A1

公开(公告)日：2018-01-04

申请号：US15702493

申请日：2017-09-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Douglas Seeman ,  Sandeep R. Bahl ,  David I. Anderson

IPC: H03K17/082 ,  H03K3/012 ,  H03K17/10 ,  H03K17/08 ,  H02H3/00 ,  H03K17/687

CPC classification number: H03K17/0822 ,  H02H3/00 ,  H03K3/012 ,  H03K17/08 ,  H03K17/102 ,  H03K2017/0806 ,  H03K2017/6875 ,  Y10T307/766

Abstract: In described examples, a first transistor has: a drain coupled to a source of a depletion-mode transistor; a source coupled to a first voltage node; and a gate coupled to a control node. A second transistor has: a drain coupled to a gate of the depletion-mode transistor; a source coupled to the first voltage node; and a gate coupled through at least one first logic device to an input node. A third transistor has: a drain coupled to the gate of the depletion-mode transistor; a source coupled to a second voltage node; and a gate coupled through at least one second logic device to the input node.

公开(公告)号：US09762230B2

公开(公告)日：2017-09-12

申请号：US14542962

申请日：2014-11-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Douglas Seeman ,  Sandeep R. Bahl ,  David I. Anderson

IPC: H03K17/082 ,  H03K17/08 ,  H02H3/00 ,  H03K3/012

CPC classification number: H03K17/0822 ,  H02H3/00 ,  H03K3/012 ,  H03K17/08 ,  H03K17/102 ,  H03K2017/0806 ,  H03K2017/6875 ,  Y10T307/766

Abstract: In described examples, a first transistor has: a drain coupled to a source of a depletion-mode transistor; a source coupled to a first voltage node; and a gate coupled to a control node. A second transistor has: a drain coupled to a gate of the depletion-mode transistor; a source coupled to the first voltage node; and a gate coupled through at least one first logic device to an input node. A third transistor has: a drain coupled to the gate of the depletion-mode transistor; a source coupled to a second voltage node; and a gate coupled through at least one second logic device to the input node.

公开(公告)号：US11356087B2

公开(公告)日：2022-06-07

申请号：US17173981

申请日：2021-02-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Douglas Seeman ,  Sandeep R. Bahl ,  David I. Anderson

IPC: H03K17/08 ,  H03K17/082 ,  H03K17/10 ,  H02H3/00 ,  H03K3/012 ,  H03K17/687

Abstract: In described examples, a first transistor has: a drain coupled to a source of a depletion-mode transistor; a source coupled to a first voltage node; and a gate coupled to a control node. A second transistor has: a drain coupled to a gate of the depletion-mode transistor; a source coupled to the first voltage node; and a gate coupled through at least one first logic device to an input node. A third transistor has: a drain coupled to the gate of the depletion-mode transistor; a source coupled to a second voltage node; and a gate coupled through at least one second logic device to the input node.

公开(公告)号：US20150137619A1

公开(公告)日：2015-05-21

申请号：US14542962

申请日：2014-11-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Douglas Seeman ,  Sandeep R. Bahl ,  David I. Anderson

IPC: H03K17/082 ,  H02H3/00 ,  H03K3/012

CPC classification number: H03K17/0822 ,  H02H3/00 ,  H03K3/012 ,  H03K17/08 ,  H03K17/102 ,  H03K2017/0806 ,  H03K2017/6875 ,  Y10T307/766

Abstract: In described examples, a first transistor has: a drain coupled to a source of a depletion-mode transistor; a source coupled to a first voltage node; and a gate coupled to a control node. A second transistor has: a drain coupled to a gate of the depletion-mode transistor; a source coupled to the first voltage node; and a gate coupled through at least one first logic device to an input node. A third transistor has: a drain coupled to the gate of the depletion-mode transistor; a source coupled to a second voltage node; and a gate coupled through at least one second logic device to the input node.

Abstract translation: 在所述示例中，第一晶体管具有：漏极，其耦合到耗尽型晶体管的源极; 耦合到第一电压节点的源极; 以及耦合到控制节点的门。 第二晶体管具有：漏极，其耦合到耗尽型晶体管的栅极; 耦合到所述第一电压节点的源极; 以及通过至少一个第一逻辑设备耦合到输入节点的门。 第三晶体管具有：漏极，其耦合到耗尽型晶体管的栅极; 耦合到第二电压节点的源极; 以及通过至少一个第二逻辑设备耦合到输入节点的门。