- Patent Title: Transistors configured for gate overbiasing and circuits therefrom
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Application No.: US14812516Application Date: 2015-07-29
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Publication No.: US09762231B2Publication Date: 2017-09-12
- Inventor: Alvin Leng Sun Loke , Bo Yu , Stephen Clifford Thilenius , Reza Jalilizeinali , Patrick Isakanian
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza, LLP/Qualcomm
- Main IPC: H03B1/00
- IPC: H03B1/00 ; H03K3/00 ; H03K17/082 ; H03K19/003 ; H03K19/0185

Abstract:
An electronic circuit and methods of operating the electronic circuit are provided. The electronic circuit includes a pull-up transistor for pulling up an input/output (I/O) node of the output circuit to a first voltage and a first isolation transistor for coupling the pull-up transistor to the I/O node. The electronic circuit also includes a pull-down transistor for pulling down the I/O node to a second voltage and a second isolation transistor for coupling the pull-down transistor to the I/O node. In the electronic circuit, the pull-up and the pull-down transistors are transistors supporting a first drain-to-source voltage and a first gate-to-source voltage, while the first and the second isolation transistors are transistors supporting the first drain-to-source voltage and a second gate-to-source voltage greater than the first gate-to-source voltage.
Public/Granted literature
- US20160269017A1 TRANSISTORS CONFIGURED FOR GATE OVERBIASING AND CIRCUITS THEREFROM Public/Granted day:2016-09-15
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