TRANSISTORS CONFIGURED FOR GATE OVERBIASING AND CIRCUITS THEREFROM
    4.
    发明申请
    TRANSISTORS CONFIGURED FOR GATE OVERBIASING AND CIRCUITS THEREFROM 有权
    晶闸管配置为栅极过渡和电路

    公开(公告)号:US20160269017A1

    公开(公告)日:2016-09-15

    申请号:US14812516

    申请日:2015-07-29

    CPC classification number: H03K17/0822 H03K19/00315 H03K19/018521

    Abstract: An electronic circuit and methods of operating the electronic circuit are provided. The electronic circuit includes a pull-up transistor for pulling up an input/output (I/O) node of the output circuit to a first voltage and a first isolation transistor for coupling the pull-up transistor to the I/O node. The electronic circuit also includes a pull-down transistor for pulling down the I/O node to a second voltage and a second isolation transistor for coupling the pull-down transistor to the I/O node. In the electronic circuit, the pull-up and the pull-down transistors are transistors supporting a first drain-to-source voltage and a first gate-to-source voltage, while the first and the second isolation transistors are transistors supporting the first drain-to-source voltage and a second gate-to-source voltage greater than the first gate-to-source voltage.

    Abstract translation: 提供电子电路和操作电子电路的方法。 电子电路包括用于将输出电路的输入/输出(I / O)节点提升到第一电压的上拉晶体管和用于将上拉晶体管耦合到I / O节点的第一隔离晶体管。 电子电路还包括用于将I / O节点下拉到第二电压的下拉晶体管和用于将下拉晶体管耦合到I / O节点的第二隔离晶体管。 在电子电路中,上拉和下拉晶体管是支持第一漏极 - 源极电压和第一栅极 - 源极电压的晶体管,而第一和第二隔离晶体管是支撑第一漏极 并且第二栅极至源极电压大于第一栅极至源极电压。

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