Invention Grant
- Patent Title: Integrated bit-line airgap formation and gate stack post clean
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Application No.: US15332910Application Date: 2016-10-24
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Publication No.: US09773695B2Publication Date: 2017-09-26
- Inventor: Vinod R. Purayath , Randhir Thakur , Shankar Venkataraman , Nitin K. Ingle
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Kilpatrick Townsend & Stockton LLP
- Main IPC: H01L21/764
- IPC: H01L21/764 ; H01L27/11568 ; H01L21/311 ; H01L29/06 ; H01L21/28 ; H01L29/66 ; H01L21/02 ; H01L21/67 ; H01L21/687 ; H01L29/788 ; H01J37/32

Abstract:
Methods of forming flash memory cells are described which incorporate air gaps for improved performance. The methods are useful for so-called “2-d flat cell” flash architectures. 2-d flat cell flash memory involves a reactive ion etch to dig trenches into multi-layers containing high work function and other metal layers. The methods described herein remove the metal oxide debris from the sidewalls of the multi-layer trench and then, without breaking vacuum, selectively remove shallow trench isolation (STI) oxidation which become the air gaps. Both the metal oxide removal and the STI oxidation removal are carried out in the same mainframe with highly selective etch processes using remotely excited fluorine plasma effluents.
Public/Granted literature
- US20170040207A1 INTEGRATED BIT-LINE AIRGAP FORMATION AND GATE STACK POST CLEAN Public/Granted day:2017-02-09
Information query
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