Invention Grant
- Patent Title: Lower-power scrambling with improved signal integrity
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Application No.: US14583623Application Date: 2014-12-27
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Publication No.: US09792246B2Publication Date: 2017-10-17
- Inventor: Ee Loon Teoh , Eng Hun Ooi , Christopher P Mozak , Brian R McFarlane
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: G06F13/42
- IPC: G06F13/42 ; G06F13/28

Abstract:
An I/O interface supports scrambling, where the scrambling can include nonlinear scrambling of the scrambling code, or dynamic bus inversion of the scrambling code, or selective switching of selected bits of the scrambling code, or a combination of these. The transmitting device includes a scrambler and the receiving device includes a descrambler. Both the scrambler and the descrambler generate a linear feedback scrambling code modified by applying one or more of the techniques mentioned above. The modified scrambling code may cause fewer than half of the scrambled output bits to be toggled with respect to a previous scrambled output. The scrambler applies the modified scrambling code to a signal to transmit. The descrambler applies the modified scrambling code to a received signal.
Public/Granted literature
- US20160188523A1 LOWER-POWER SCRAMBLING WITH IMPROVED SIGNAL INTEGRITY Public/Granted day:2016-06-30
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