公开(公告)号：US09792246B2

公开(公告)日：2017-10-17

申请号：US14583623

申请日：2014-12-27

Applicant: Intel Corporation

Inventor： Ee Loon Teoh ,  Eng Hun Ooi ,  Christopher P Mozak ,  Brian R McFarlane

IPC: G06F13/42 ,  G06F13/28

CPC classification number: G06F13/4282 ,  G06F13/1668 ,  G06F13/28 ,  G06F21/79 ,  Y02D10/14 ,  Y02D10/151

Abstract: An I/O interface supports scrambling, where the scrambling can include nonlinear scrambling of the scrambling code, or dynamic bus inversion of the scrambling code, or selective switching of selected bits of the scrambling code, or a combination of these. The transmitting device includes a scrambler and the receiving device includes a descrambler. Both the scrambler and the descrambler generate a linear feedback scrambling code modified by applying one or more of the techniques mentioned above. The modified scrambling code may cause fewer than half of the scrambled output bits to be toggled with respect to a previous scrambled output. The scrambler applies the modified scrambling code to a signal to transmit. The descrambler applies the modified scrambling code to a received signal.

公开(公告)号：US11023244B2

公开(公告)日：2021-06-01

申请号：US15713974

申请日：2017-09-25

Applicant: Intel Corporation

Inventor： Ee Loon Teoh ,  Eng Hun Ooi ,  Roger K. Cheng

IPC: G06F9/38 ,  G06F13/20 ,  G06F13/42 ,  G06F1/32 ,  G06F11/07 ,  G06F13/40 ,  G06F11/30

Abstract: In one embodiment, a link training controller is to train a link. The link training controller may be configured to: update a first link parameter of a link setting for the link to a first value; write data to the memory; read the data from the memory using the first value of the first link parameter; and in response to a determination that the data read from the memory does not match the data written to the memory, send an in-band link recovery command to the memory via the link to cause the memory to participate in a link recovery protocol with the apparatus. Other embodiments are described and claimed.

公开(公告)号：US20160188523A1

公开(公告)日：2016-06-30

申请号：US14583623

申请日：2014-12-27

Applicant: Intel Corporation

Inventor： Ee Loon Teoh ,  Eng Hun Ooi ,  Christopher P. Mozak ,  Brian R. McFarlane

IPC: G06F13/42 ,  G06F13/28

CPC classification number: G06F13/4282 ,  G06F13/1668 ,  G06F13/28 ,  G06F21/79 ,  Y02D10/14 ,  Y02D10/151

Abstract: An I/O interface supports scrambling, where the scrambling can include nonlinear scrambling of the scrambling code, or dynamic bus inversion of the scrambling code, or selective switching of selected bits of the scrambling code, or a combination of these. The transmitting device includes a scrambler and the receiving device includes a descrambler. Both the scrambler and the descrambler generate a linear feedback scrambling code modified by applying one or more of the techniques mentioned above. The modified scrambling code may cause fewer than half of the scrambled output bits to be toggled with respect to a previous scrambled output. The scrambler applies the modified scrambling code to a signal to transmit. The descrambler applies the modified scrambling code to a received signal.

Abstract translation: I / O接口支持加扰，其中加扰可以包括扰码的非线性加扰或扰码的动态总线反转，或扰码的选定位的选择性切换，或这些的组合。 发送设备包括加扰器，并且接收设备包括解扰器。 加扰器和解扰器都产生通过应用上述一种或多种技术修改的线性反馈扰码。 经修改的扰码可能导致少于一半的加扰输出比特相对于先前的加扰输出被切换。 扰频器将修改的扰码应用于要发送的信号。 解扰器将修改的扰码应用于接收信号。