Invention Grant
- Patent Title: Ramping inhibit voltage during memory programming
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Application No.: US15183582Application Date: 2016-06-15
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Publication No.: US09792997B2Publication Date: 2017-10-17
- Inventor: Shantanu R. Rajwade , Pranav Kalavade , Neal R. Mielke , Krishna K. Parat , Shyam Sunder Raghunathan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C16/34 ; G11C16/10 ; G11C16/04 ; G11C16/08

Abstract:
The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.
Public/Granted literature
- US20160372207A1 RAMPING INHIBIT VOLTAGE DURING MEMORY PROGRAMMING Public/Granted day:2016-12-22
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