公开(公告)号：US09740437B2

公开(公告)日：2017-08-22

申请号：US14672084

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Neal R. Mielke ,  Mark Anthony Golez ,  David J. Pelster ,  Paul D. Ruby ,  Xin Guo

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0679 ,  G06F3/0616 ,  G06F3/0652 ,  G06F12/0246

Abstract: Methods and apparatus related to a mechanism for quickly adapting garbage collection resource allocation for an incoming I/O (Input/Output) workload are described. In one embodiment, non-volatile memory stores data corresponding to a first workload and a second workload. Allocation of one or more resources in the non-volatile memory is determined based at least in part on a determination of an average validity of one or more blocks, where the one or more candidate bands are to be processed during operation of the first workload or the second workload. Other embodiments are also disclosed and claimed.

公开(公告)号：US09792997B2

公开(公告)日：2017-10-17

申请号：US15183582

申请日：2016-06-15

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Neal R. Mielke ,  Krishna K. Parat ,  Shyam Sunder Raghunathan

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10

Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.

公开(公告)号：US10658053B2

公开(公告)日：2020-05-19

申请号：US15715980

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Neal R. Mielke ,  Krishna K. Parat ,  Shyam Sunder Raghunathan

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/08

Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.

公开(公告)号：US20160372207A1

公开(公告)日：2016-12-22

申请号：US15183582

申请日：2016-06-15

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Neal R. Mielke ,  Krishna K. Parat ,  Shyam Sunder Raghunathan

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10

Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.

公开(公告)号：US20160283161A1

公开(公告)日：2016-09-29

申请号：US14672084

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Neal R. Mielke ,  Mark Anthony Golez ,  David J. Pelster ,  Paul D. Ruby ,  Xin Guo

IPC: G06F3/06

CPC classification number: G06F3/0679 ,  G06F3/0616 ,  G06F3/0652 ,  G06F12/0246

Abstract: Methods and apparatus related to a mechanism for quickly adapting garbage collection resource allocation for an incoming I/O (Input/Output) workload are described. In one embodiment, non-volatile memory stores data corresponding to a first workload and a second workload. Allocation of one or more resources in the non-volatile memory is determined based at least in part on a determination of an average validity of one or more blocks, where the one or more candidate bands are to be processed during operation of the first workload or the second workload. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与用于快速适应输入I / O（输入/输出）工作负载的垃圾收集资源分配的机制相关的方法和装置。 在一个实施例中，非易失性存储器存储对应于第一工作负载和第二工作负载的数据。 至少部分地基于一个或多个块的平均有效性的确定来确定非易失性存储器中的一个或多个资源的分配，其中在第一工作负载的操作期间处理一个或多个候选频带， 第二个工作量。 还公开并要求保护其他实施例。