Invention Grant
- Patent Title: Use of grapho-epitaxial directed self-assembly applications to precisely cut logic lines
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Application No.: US15230974Application Date: 2016-08-08
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Publication No.: US09793137B2Publication Date: 2017-10-17
- Inventor: Mark H. Somervell , Benjamen M. Rathsack
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Wood Herron & Evans LLP
- Main IPC: H01L21/302
- IPC: H01L21/302 ; H01L21/3213 ; H01L21/308 ; H01L21/027 ; H01L21/033 ; G03F7/00 ; G03F7/09

Abstract:
A method for patterning topography is provided. A substrate is provided with a plurality of lines. The method includes aligning and preparing a first directed self-assembly (DSA) pattern overlying the lines, transferring the first pattern to form first line cuts, aligning and preparing a second DSA pattern overlying the lines, and transferring the second pattern to form second line cuts. The DSA patterns include trenches and holes of diameter d, and each comprise a block copolymer having HCP morphology, a characteristic dimension Lo approximately equal to the line pitch, and a minority phase of the diameter d. The trenches are wet by a majority phase of the block copolymer and guide formation of the holes. The aligning and preparation of the DSA patterns include overlapping the two sets of trenches such that areas between holes of one pattern and adjacent holes of the other pattern are shared by adjacent trenches.
Public/Granted literature
- US20160343588A1 USE OF GRAPHO-EPITAXIAL DIRECTED SELF-ASSEMBLY APPLICATIONS TO PRECISELY CUT LOGIC LINES Public/Granted day:2016-11-24
Information query
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