公开(公告)号：US09793137B2

公开(公告)日：2017-10-17

申请号：US15230974

申请日：2016-08-08

Applicant: Tokyo Electron Limited

Inventor： Mark H. Somervell ,  Benjamen M. Rathsack

IPC: H01L21/302 ,  H01L21/3213 ,  H01L21/308 ,  H01L21/027 ,  H01L21/033 ,  G03F7/00 ,  G03F7/09

CPC classification number: H01L21/32139 ,  G03F7/0002 ,  G03F7/091 ,  H01L21/0273 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/76838

Abstract: A method for patterning topography is provided. A substrate is provided with a plurality of lines. The method includes aligning and preparing a first directed self-assembly (DSA) pattern overlying the lines, transferring the first pattern to form first line cuts, aligning and preparing a second DSA pattern overlying the lines, and transferring the second pattern to form second line cuts. The DSA patterns include trenches and holes of diameter d, and each comprise a block copolymer having HCP morphology, a characteristic dimension Lo approximately equal to the line pitch, and a minority phase of the diameter d. The trenches are wet by a majority phase of the block copolymer and guide formation of the holes. The aligning and preparation of the DSA patterns include overlapping the two sets of trenches such that areas between holes of one pattern and adjacent holes of the other pattern are shared by adjacent trenches.

公开(公告)号：US09711419B2

公开(公告)日：2017-07-18

申请号：US14833044

申请日：2015-08-22

Applicant: Tokyo Electron Limited

Inventor： Carlos A. Fonseca ,  Benjamen M. Rathsack ,  Jeffrey Smith ,  Anton J. deVilliers ,  Lior Huli ,  Teruhiko Kodama ,  Joshua S. Hooge

IPC: H01B13/00 ,  H01L21/66 ,  H01L21/306 ,  G03F7/20 ,  H01L21/027

CPC classification number: H01L22/12 ,  G03F7/70783 ,  H01L21/0274 ,  H01L21/30625 ,  H01L22/20

Abstract: Embodiments described relate to a method and apparatus for reducing lithographic distortion. A backside of a semiconductor substrate may be texturized. Then a lithographic process may be performed on the semiconductor substrate having the texturized backside.

公开(公告)号：US20160343588A1

公开(公告)日：2016-11-24

申请号：US15230974

申请日：2016-08-08

Applicant: Tokyo Electron Limited

Inventor： Mark H. Somervell ,  Benjamen M. Rathsack

IPC: H01L21/3213 ,  H01L21/027 ,  H01L21/033 ,  H01L21/308

CPC classification number: H01L21/32139 ,  G03F7/0002 ,  G03F7/091 ,  H01L21/0273 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/76838

Abstract: A method for patterning topography is provided. A substrate is provided with a plurality of lines. The method includes aligning and preparing a first directed self-assembly (DSA) pattern overlying the lines, transferring the first pattern to form first line cuts, aligning and preparing a second DSA pattern overlying the lines, and transferring the second pattern to form second line cuts. The DSA patterns include trenches and holes of diameter d, and each comprise a block copolymer having HCP morphology, a characteristic dimension Lo approximately equal to the line pitch, and a minority phase of the diameter d. The trenches are wet by a majority phase of the block copolymer and guide formation of the holes. The aligning and preparation of the DSA patterns include overlapping the two sets of trenches such that areas between holes of one pattern and adjacent holes of the other pattern are shared by adjacent trenches.

Abstract translation: 提供了一种用于图案形貌的方法。 基板设置有多条线。 该方法包括对准和制备覆盖线的第一定向自组装（DSA）图案，传送第一图案以形成第一线切割，对准和制备覆盖线的第二DSA图案，以及传送第二图案以形成第二线 削减 DSA图案包括直径d的沟槽和孔，并且每个包含具有HCP形态，大约等于线间距的特征尺寸Lo和直径d的少数相位的嵌段共聚物。 沟槽被嵌段共聚物的多数相湿润并引导孔的形成。 DSA图案的对准和准备包括重叠两组沟槽，使得一个图案的孔和另一图案的相邻孔之间的区域由相邻的沟槽共享。

公开(公告)号：US20160043007A1

公开(公告)日：2016-02-11

申请号：US14833044

申请日：2015-08-22

Applicant: Tokyo Electron Limited

Inventor： Carlos A. Fonseca ,  Benjamen M. Rathsack ,  Jeffrey Smith ,  Anton J. deVilliers ,  Lior Huli ,  Teruhiko Kodama ,  Joshua S. Hooge

IPC: H01L21/66 ,  H01L21/306 ,  H01L21/268

CPC classification number: H01L22/12 ,  G03F7/70783 ,  H01L21/0274 ,  H01L21/30625 ,  H01L22/20

Abstract: Embodiments described relate to a method and apparatus for reducing lithographic distortion. A backside of a semiconductor substrate may be texturized. Then a lithographic process may be performed on the semiconductor substrate having the texturized backside.

公开(公告)号：US20140273522A1

公开(公告)日：2014-09-18

申请号：US14202642

申请日：2014-03-10

Applicant: Tokyo Electron Limited

Inventor： Benjamen M. Rathsack

IPC: H01L21/02

CPC classification number: H01L21/02269 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  G03F7/40 ,  H01L21/0271 ,  H01L21/0337

Abstract: A method of forming a patterned substrate includes casting a layer of a block copolymer having an intrinsic glass transition temperature Tg, on a substrate to form a layered substrate. The method also includes heating the layered substrate at an annealing temperature, which is greater than about 50° C. above the intrinsic glass transition temperature Tg of the block copolymer, in a first atmosphere. The method further includes thermally quenching the layered substrate to a quenching temperature lower than the intrinsic glass transition temperature Tg, at a rate of greater than about 50° C./minute in a second atmosphere. The method further includes controlling an oxygen content in the first and second atmospheres to a level equal to or less than about 8 ppm to maintain the annealing and quenching temperatures below a thermal degradation temperature Td of the block copolymer.

Abstract translation: 形成图案化衬底的方法包括在衬底上浇铸具有本征玻璃化转变温度Tg的嵌段共聚物层以形成层状衬底。 该方法还包括在第一气氛中以高于嵌段共聚物的本征玻璃化转变温度Tg高于约50℃的退火温度加热层状基材。 该方法还包括在第二气氛中以大于约50℃/分钟的速率将层状衬底热淬火至低于本征玻璃化转变温度Tg的淬火温度。 该方法还包括将第一和第二气氛中的氧含量控制在等于或小于约8ppm的水平以保持退火和淬火温度低于嵌段共聚物的热降解温度Td。

公开(公告)号：US10170354B2

公开(公告)日：2019-01-01

申请号：US15096314

申请日：2016-04-12

Applicant: Tokyo Electron Limited

Inventor： Mark H. Somervell ,  Benjamen M. Rathsack

IPC: H01L21/02 ,  H01L21/31 ,  H01L21/762 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/311

Abstract: A method for partially filling an open feature on a substrate includes receiving a substrate having a layer with at least one open feature formed therein, wherein the open feature penetrates into the layer from an upper surface and includes sidewalls extending to a bottom of the open feature. The open feature is overfilled with an organic coating that covers the upper surface of the layer and extends to the bottom of the open feature. The method further includes removing a portion of the organic coating to expose the upper surface of the layer and recessing the organic coating to a pre-determined depth from the upper surface to create an organic coating plug of pre-determined thickness at the bottom of the open feature, and converting the chemical composition of the organic coating plug to create an inorganic plug.

公开(公告)号：US20180096905A1

公开(公告)日：2018-04-05

申请号：US15724632

申请日：2017-10-04

Applicant: Tokyo Electron Limited

Inventor： Ryan L. Burns ,  Benjamen M. Rathsack ,  Mark H. Somervell ,  Makoto Muramatsu

IPC: H01L21/66 ,  H01L21/3105 ,  H01L21/02 ,  G06F17/50

CPC classification number: H01L22/20 ,  G06F17/5009 ,  H01L21/02282 ,  H01L21/31055 ,  H01L22/12

Abstract: Described herein are technologies to facilitate device fabrication, especially those that involve spin-on coatings of a substrate (e.g., wafer). More particularly, technologies described herein facilitate the planarization (i.e., flatness) of spin-on coatings during the device fabrication to form a uniformly planar film or layer on the substrate. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

公开(公告)号：US20160358786A1

公开(公告)日：2016-12-08

申请号：US15171188

申请日：2016-06-02

Applicant: Tokyo Electron Limited

Inventor： Joshua S. Hooge ,  Benjamen M. Rathsack ,  Michael A. Carcasi ,  Mark H. Somervell ,  Ian J. Brown ,  Wallace P. Printz

IPC: H01L21/3105 ,  H01L21/027 ,  H01L21/02 ,  H01L21/311 ,  H01L21/67 ,  H01L21/68

CPC classification number: H01L21/31133 ,  H01L21/31058 ,  H01L21/67115 ,  H01L21/6776

Abstract: Systems and methods for SOC planarization are described. In an embodiment, an apparatus for SOC planarization includes a substrate holder configured to support a microelectronic substrate. Additionally, the apparatus may include a light source configured to emit ultraviolet (UV) light toward a surface of the microelectronic substrate. In an embodiment, the apparatus may also include an isolation window disposed between the light source and the microelectronic substrate. Also, the apparatus may include a gas distribution unit configured to inject gas in a region between the isolation window and the microelectronic substrate. Furthermore, the apparatus may include an etchback leveling component configured to reduce non-uniformity of a UV light treatment of the microelectronic substrate.

Abstract translation: 描述了用于SOC平坦化的系统和方法。 在一个实施例中，用于SOC平坦化的装置包括被配置为支撑微电子衬底的衬底保持器。 另外，该装置可以包括被配置为朝向微电子基板的表面发射紫外（UV）光的光源。 在一个实施例中，该装置还可以包括设置在光源和微电子衬底之间的隔离窗口。 此外，该装置可以包括配置成在隔离窗和微电子基板之间的区域中注入气体的气体分配单元。 此外，该装置可以包括构造成减少微电子衬底的UV光处理的不均匀性的回蚀整平部件。

公开(公告)号：US09349604B2

公开(公告)日：2016-05-24

申请号：US14517270

申请日：2014-10-17

Applicant: Tokyo Electron Limited

Inventor： Benjamen M. Rathsack ,  Mark H. Somervell

IPC: G03F7/40 ,  G03F7/00 ,  G03F7/16 ,  G03F7/26 ,  H01L21/308 ,  G03F7/42 ,  H01L21/027 ,  G03F7/09 ,  H01L21/033 ,  H01L21/3213

CPC classification number: G03F7/0002 ,  G03F7/091 ,  G03F7/165 ,  G03F7/40 ,  G03F7/42 ,  H01L21/0273 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31116 ,  H01L21/32139

Abstract: A method is provided for forming a patterned topography on a substrate. The substrate is provided with features formed atop that constitute an existing topography, and a template for directed self-assembly (DSA) surrounds the exposed topography. Further to the method, the template is filled with a block copolymer (BCP) to cover the exposed topography, and then the BCP is annealed within the template to drive self-assembly in alignment with the topography. Developing the annealed BCP exposes a DSA pattern immediately overlying the topography.

Abstract translation: 提供了一种在衬底上形成图案形貌的方法。 衬底具有形成在顶部的构成现有形貌的特征，以及用于定向自组装（DSA）的模板围绕暴露的形貌。 除了该方法之外，模板用嵌段共聚物（BCP）填充以覆盖暴露的形貌，然后在模板内对BCP进行退火以驱动与地形对准的自组装。 开发退火的BCP暴露了立即覆盖地形的DSA模式。

公开(公告)号：US10534266B2

公开(公告)日：2020-01-14

申请号：US15445738

申请日：2017-02-28

Applicant: TOKYO ELECTRON LIMITED

Inventor： Michael A. Carcasi ,  Joshua S. Hooge ,  Benjamen M. Rathsack ,  Seiji Nagahara

IPC: G03F7/038 ,  G03F7/039 ,  G03F7/20 ,  G03F7/09 ,  G03F7/30 ,  G03F7/26 ,  G03F7/38 ,  G03F7/11 ,  H01L21/027 ,  G03F7/004

Abstract: The disclosure herein describes methods for Photosensitized Chemically Amplified Resist Chemicals (PS-CAR) to pattern light sensitive films on a semiconductor substrate. In one embodiment, a two-step exposure process may generate higher acid concentration regions within a photoresist layer. The PS-CAR chemicals may include photoacid generators (PAGs) and photosensitizer elements that enhance the decomposition of the PAGs into acid. The first exposure may be a patterned EUV exposure that generates an initial amount of acid and photosensitizer. The second exposure may be a non-EUV flood exposure that excites the photosensitizer which increases the acid generation rate where the photosensitizer is located on the substrate. The distribution of energy during the exposures may be optimized by using certain characteristics (e.g., thickness, index of refraction, doping) of the photoresist layer, an underlying layer, and/or an overlying layer.