Invention Grant
- Patent Title: Field effect transistor structure with abrupt source/drain junctions
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Application No.: US15461427Application Date: 2017-03-16
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Publication No.: US09793373B2Publication Date: 2017-10-17
- Inventor: Anand S. Murthy , Robert S. Chau , Patrick Morrow , Chia-Hong Jan , Paul Packan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/66 ; H01L29/08 ; H01L29/06 ; H01L29/78 ; H01L29/165

Abstract:
Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.
Public/Granted literature
- US20170186855A1 FIELD EFFECT TRANSISTOR STRUCTURE WITH ABRUPT SOURCE/DRAIN JUNCTIONS Public/Granted day:2017-06-29
Information query
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