Invention Grant
- Patent Title: Apparatus and method for increasing resilience to raw bit error rate
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Application No.: US14557070Application Date: 2014-12-01
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Publication No.: US09798622B2Publication Date: 2017-10-24
- Inventor: Ravi H. Motwani
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP.
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G06F12/02 ; H03M13/29 ; H03M13/15

Abstract:
Described is an apparatus which comprises: a first encoder to encode data with a first error correction scheme to generate a set of codewords, each codeword of the set having a data portion and a corresponding parity portion, and each codeword of the set to be stored in a separate memory bank of a memory block; and a second encoder to encode the data portions of each codeword of the set with a second error correction scheme, the second encoder to generate a combined codeword having a data portion and a corresponding parity portion, wherein the corresponding parity portion of the combined codeword is to be stored in an additional memory bank of the memory block.
Public/Granted literature
- US20160156372A1 APPARATUS AND METHOD FOR INCREASING RESILIENCE TO RAW BIT ERROR RATE Public/Granted day:2016-06-02
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