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公开(公告)号：US12126361B2
公开(公告)日：2024-10-22
申请号：US17700022
申请日：2022-03-21
Applicant: Intel Corporation
Inventor： Poovaiah M. Palangappa , Zion S. Kwok , Ravi H. Motwani
CPC classification number: H03M13/159 , G06F3/0619 , G06F3/0644 , G06F3/0659 , G06F3/0679 , H03M13/1105 , H03M13/1177
Abstract: A memory controller system includes error correction circuitry and erasure decoder circuitry. A retry flow is triggered when the memory controller's error checking and correction (ECC) detects an uncorrectable codeword. Error correction circuitry generates erasure codewords from the codeword with uncorrectable errors. The memory controller computes the syndrome weight of the erasure codewords. For example, the erasure decoder circuitry receives the erasure codewords and computes the syndrome weights. Error correction circuitry orders the erasure codewords based on their corresponding syndrome weights. Then error correction circuitry selects a subset of the codewords, and sends them to erasure decoder circuitry. Erasure decoder circuitry receives the selected codewords and decodes them.
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公开(公告)号：US20210165712A1
公开(公告)日：2021-06-03
申请号：US17171430
申请日：2021-02-09
Applicant: Intel Corporation
Inventor： Debarnab Mitra , Zion S. Kwok , Ravi H. Motwani
Abstract: An embodiment of an electronic apparatus comprises one or more substrates, and logic coupled to the one or more substrates, the logic to detect unreliable messages between check nodes and variable nodes in association with an error correction operation, determine respective degrees of unreliability for the unreliable messages, and reduce an influence of the unreliable messages on the error correction operation, as compared to an influence of reliable messages between the check nodes and the variables nodes, based on the determined respective degrees of unreliability. Other embodiments are disclosed and claimed.
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公开(公告)号：US20200293696A1
公开(公告)日：2020-09-17
申请号：US16885726
申请日：2020-05-28
Applicant: Intel Corporation
Inventor： Ravi H. Motwani , Santhosh Kumar Vanaparthy
Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to generate a pseudo-random sequence of bits, permute one or more bits of binary unscrambled data, and generate scrambled data based on an exclusive-or operation between the pseudo-random sequence of bits and the permuted data. Other embodiments are disclosed and claimed.
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公开(公告)号：US10176042B2
公开(公告)日：2019-01-08
申请号：US15438655
申请日：2017-02-21
Applicant: INTEL CORPORATION
Inventor： Andre Lei , Scott Nelson , Zion S. Kwok , Ravi H. Motwani
Abstract: Provided are a method, system, and apparatus using reliability information from multiple storage units and a parity storage unit to recover data for a failed one of the storage units. A decoding operation of the codeword is performed in each of the storage units comprising the data storage units other than the target data storage unit and the parity storage unit to produce reliability information. In response to the decoding operation failing for at least one additional failed storage unit comprising the data and/or parity storage units other than the target data storage unit that failed to decode, reliability information is obtained for the data portion of the at least one additional failed storage unit. The reliability information obtained from the storage units other than the target data storage unit is used to produce corrected data for the data unit in the target data storage unit.
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5.发明申请公开(公告)号：US20160087646A1
公开(公告)日：2016-03-24
申请号：US14490307
申请日：2014-09-18
Applicant: Intel Corporation
Inventor： Ravi H. Motwani , Pranav Kalavade
IPC: H03M7/02
Abstract: Described is an apparatus for converting binary data to ternary and back such that the apparatus comprises: a first look-up table (LUT) having a mapping of 19 binary bits to 12 ternary trits; and a first logic to receive a binary input and to convert the binary input to a ternary output according to the first LUT.
Abstract translation: 描述了一种用于将二进制数据转换为三进制和反向的装置，使得该装置包括：具有19个二进制位到12个三进制位映射的第一查找表（LUT） 以及接收二进制输入并根据第一LUT将二进制输入转换为三进制输出的第一逻辑。
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Patent Agency Ranking
公开(公告)号：US09250990B2
公开(公告)日：2016-02-02
申请号：US14129070
申请日：2013-09-24
Applicant: INTEL CORPORATION
Inventor： Ravi H. Motwani , Kiran Pangal
CPC classification number: G06F11/073 , G06F11/076 , G06F11/0772 , G06F11/1048
Abstract: Methods, apparatuses, and systems related to use of error correction pointers (ECPs) to handle hard errors in memory are described herein. In embodiments, a read module of a memory controller may read a codeword stored in a memory. The read module may determine a number of hard errors in the codeword. Responsive to a determination that the number of hard errors exceeds a threshold, the read module may store ECP information associated with the hard errors. The read module may include an error correction code (ECC) module to perform an ECC process on the codeword. The read module may use the ECP information to decode the codeword to recover the data responsive to a determination that the ECC process failed. Other embodiments may be described and claimed.
Abstract translation: 这里描述了使用纠错指针（ECP）来处理存储器中的硬错误的方法，装置和系统。 在实施例中，存储器控制器的读取模块可以读取存储在存储器中的代码字。 读取模块可以确定码字中的许多硬错误。 响应于确定硬错误的数量超过阈值，读取模块可以存储与硬错误相关联的ECP信息。 读取模块可以包括用于对码字执行ECC处理的纠错码（ECC）模块。 读取模块可以使用ECP信息来解码码字以响应于ECC过程失败的确定来恢复数据。 可以描述和要求保护其他实施例。
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公开(公告)号：US20150149857A1
公开(公告)日：2015-05-28
申请号：US14091757
申请日：2013-11-27
Applicant: Intel Corporation
Inventor： Ravi H. Motwani , Kiran Pangal
CPC classification number: G06F11/1008 , G06F11/10 , G06F11/1004 , G06F11/1048 , H03M13/05 , H03M13/1102 , H03M13/1515 , H03M13/152 , H03M13/23 , H03M13/2957
Abstract: Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a controller comprises logic to receive a read request from a host device for data stored in a memory, retrieve the data and an associated error correction codeword, send the data to a host device, apply an error correction routine to decode the error correction codeword retrieved with the data, and in response to an error in the error correction codeword, send a location of data associated with the error to the host device. Other embodiments are also disclosed and claimed.
Abstract translation: 描述了存储器中用于纠错的装置，系统和方法。 在一个实施例中，控制器包括从主机设备接收存储在存储器中的数据的读取请求的逻辑，检索数据和相关联的纠错码字，将数据发送到主机设备，应用纠错例程来解码 使用数据检索的纠错码字，并且响应于纠错码字中的错误，向主机设备发送与该错误相关联的数据的位置。 还公开并要求保护其他实施例。
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公开(公告)号：US20240119287A1
公开(公告)日：2024-04-11
申请号：US18545762
申请日：2023-12-19
Applicant: Intel Corporation
Inventor： Ravi H. Motwani , Ke Ding , Jian Zhang , Chendi Xue , Poovaiah Manavattira Palangappa , Rita Brugarolas Brufau , Xinyao Wang , Yu Zhou , Aasavari Dhananjay Kakne
IPC: G06N3/08
CPC classification number: G06N3/08
Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed that include interface circuitry, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to associate first datapoints of a first feature with a first node, associate second datapoints of a second feature with a second node, construct a graph from the first datapoints and the second datapoints, and perform a comparison of a graph accuracy with a baseline accuracy.
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公开(公告)号：US10707901B2
公开(公告)日：2020-07-07
申请号：US16242155
申请日：2019-01-08
Applicant: Intel Corporation
Inventor： Poovaiah M Palangappa , Ravi H. Motwani , Santhosh K. Vanaparthy
Abstract: Examples include techniques for improving low-density parity check decoder performance for a binary asymmetric channel in a multi-die scenario. Examples include logic for execution by circuitry to decode an encoded codeword of data received from a memory having a plurality of dies, bits of the encoded codeword stored across the plurality of dies, using predetermined log-likelihood ratios (LLRs) to produce a decoded codeword, return the decoded codeword when the decoded codeword is correct, and repeat the decoding using the predetermined LLRs when the decoded codeword is not correct, up to a first number of times when the decoded codeword is not correct. When a correct decoded codeword is not produced using predetermined LLRs, further logic may be executed to estimate the LLRs for a plurality of buckets of the plurality of dies, normalize magnitudes of the estimated LLRs, decode the encoded codeword using the normalized estimated LLRs to produce a decoded codeword, return the decoded codeword when the decoded codeword is correct, and repeat the decoding using the normalized estimated LLRs when the decoded codeword is not correct, up to a second number of times when the decoded codeword is not correct.
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10.发明授权公开(公告)号：US10599515B2
公开(公告)日：2020-03-24
申请号：US15851596
申请日：2017-12-21
Applicant: INTEL CORPORATION
Inventor： Pranav Kalavade , Ravi H. Motwani
Abstract: A non-volatile memory unit receives a request from a controller to read encoded data stored in a non-volatile memory of the non-volatile memory unit. In response to determining by logic included in the non-volatile memory unit that the controller is estimated to be able to successfully decode the encoded data more than a predetermined percentage of times, the encoded data is transferred from the non-volatile memory unit to the controller.
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