Invention Grant
- Patent Title: Circuit for adjusting a select gate voltage of a non-volatile memory during erasure of memory cells based on a well voltage
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Application No.: US14471769Application Date: 2014-08-28
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Publication No.: US09805803B2Publication Date: 2017-10-31
- Inventor: Shuo-Nan Hung , Shin-Jang Shen , Wei-Jen Chen
- Applicant: MACRONIX International Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: MACRONIX International Co., Ltd.
- Current Assignee: MACRONIX International Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: J.C. Patents
- Main IPC: G11C16/14
- IPC: G11C16/14 ; G11C16/08

Abstract:
A circuit for adjusting a select gate voltage of a non-volatile memory is provided. The circuit includes a well, a select gate, an adjustment unit, and a switch. There is a capacitive coupling between the well and the select gate. The adjustment unit generates a driving voltage for the select gate. The switch is coupled in series with the adjustment unit between the select gate and the well.
Public/Granted literature
- US20160064086A1 CIRCUIT AND METHOD FOR ADJUSTING SELECT GATE VOLTAGE OF NON-VOLATILE MEMORY Public/Granted day:2016-03-03
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