Circuit for adjusting a select gate voltage of a non-volatile memory during erasure of memory cells based on a well voltage
Abstract:
A circuit for adjusting a select gate voltage of a non-volatile memory is provided. The circuit includes a well, a select gate, an adjustment unit, and a switch. There is a capacitive coupling between the well and the select gate. The adjustment unit generates a driving voltage for the select gate. The switch is coupled in series with the adjustment unit between the select gate and the well.
Information query
Patent Agency Ranking
0/0