Invention Grant
- Patent Title: Device isolator with reduced parasitic capacitance
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Application No.: US14680211Application Date: 2015-04-07
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Publication No.: US09806148B2Publication Date: 2017-10-31
- Inventor: Raja Selvaraj , Anant Shankar Kamath , Byron Lovell Williams , Thomas D. Bonifield , John Kenneth Arch
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L27/06 ; H01L21/761 ; H01L49/02 ; H01L21/265 ; H01L23/522 ; H01L23/528 ; H01L23/00

Abstract:
Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.
Public/Granted literature
- US20160300907A1 Device Isolator with Reduced Parasitic Capacitance Public/Granted day:2016-10-13
Information query
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