公开(公告)号：US11495658B2

公开(公告)日：2022-11-08

申请号：US16435095

申请日：2019-06-07

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Elizabeth Costner Stewart ,  Jeffrey A. West ,  Thomas D. Bonifield

IPC分类号： H01L49/02 ,  H01L27/07 ,  H01L29/06 ,  H01L23/522

摘要： An electronic device, e.g. integrated circuit, has top and bottom metal plates located over a substrate, the bottom plate located between the top plate and the substrate. A high-stress silicon dioxide layer is located between the bottom plate and the substrate. At least one low-stress silicon dioxide layer is located between the top plate and the bottom plate.

公开(公告)号：US20200058485A1

公开(公告)日：2020-02-20

申请号：US16542628

申请日：2019-08-16

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Jeffrey Alan West ,  Adrian Salinas ,  Elizabeth C. Stewart ,  Dhanoop Varghese ,  Thomas D. Bonifield

IPC分类号： H01L21/02 ,  H01L49/02

摘要： An integrated circuit a semiconductor substrate includes a device die with includes transistors configured to execute an electrical function. A first interconnect layer of the device die is configured to route electrical signals or power to terminals of the transistors. An interlevel dielectric (ILD) layer is located over the interconnect layer. A metal electrode located over the ILD layer. A dielectric barrier layer is located between the ILD layer and the metal electrode. A scribe seal surrounds the device die. A first opening within the dielectric barrier layer surrounds the metal electrode. Second and third openings within the dielectric barrier layer are located between the first opening and the scribe seal.

公开(公告)号：US10147784B2

公开(公告)日：2018-12-04

申请号：US15606158

申请日：2017-05-26

申请人： Texas Instruments Incorporated

发明人： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC分类号： H01L49/02 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L27/06

摘要： A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

公开(公告)号：US20160300907A1

公开(公告)日：2016-10-13

申请号：US14680211

申请日：2015-04-07

申请人： Texas Instruments Incorporated

发明人： Raja Selvaraj ,  Anant Shankar Kamath ,  Byron Lovell Williams ,  Thomas D. Bonifield ,  John Kenneth Arch

IPC分类号： H01L29/06 ,  H01L21/768 ,  H01L21/761 ,  H01L21/265 ,  H01L27/06 ,  H01L49/02

CPC分类号： H01L29/0646 ,  H01L21/265 ,  H01L21/761 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5286 ,  H01L24/05 ,  H01L27/0676 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/48463

摘要： Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.

摘要翻译： 具有降低的有效寄生电容的集成电路的隔离器结构。 公开的实施例包括具有形成电容器或电感变压器的并联导电元件的隔离器结构，覆盖包括形成在第二导电类型的槽区域内的第一导电类型的阱区的半导体结构。 槽区被掺杂区域和第一导电类型的掩埋掺杂层围绕，形成与衬底串联的多个二极管。 串联二极管的结电容具有降低隔离器明显的寄生电容的作用。

公开(公告)号：US20160163785A1

公开(公告)日：2016-06-09

申请号：US15045449

申请日：2016-02-17

申请人： Texas Instruments Incorporated

发明人： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC分类号： H01L49/02

CPC分类号： H01L28/91 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823481 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L29/0692 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/7833

摘要： A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

摘要翻译： 微电子器件包含具有高电压节点和低电压节点的高电压分量。 高电压节点通过微电子器件的基板的表面处的高压节点和低电压元件之间的主电介质与低电压节点隔离。 低压隙电介质层设置在高电压节点和主电介质之间。 低带隙电介质层含有至少一个带隙能量小于主电介质带隙能量的子层。 低带隙电介质层围绕高压节点连续延伸超过高压节点。 较低带隙电介质层具有围绕高电压节点的隔离断裂，距离高压节点的至少两倍于低带隙电介质层的厚度。

公开(公告)号：US11205695B2

公开(公告)日：2021-12-21

申请号：US15850999

申请日：2017-12-21

申请人： Texas Instruments Incorporated

发明人： Elizabeth C. Stewart ,  Jeffrey Alan West ,  Thomas D. Bonifield ,  Jay Sung Chun ,  Byron Lovell Williams

IPC分类号： H01L21/02 ,  H01L23/522 ,  H01L49/02 ,  H01L21/027 ,  H01L21/311

摘要： Methods of fabricating a thick oxide feature on a semiconductor wafer include forming a oxide layer having a thickness of at least six micrometers and depositing a photoresist layer on the oxide layer. The oxide layer has a first etch rate of X with a given etchant, the photoresist layer has a second etch rate of Y with the given etchant and the ratio of X:Y is less than 4:1. Prior to etching the photoresist layer and the oxide layer, the photoresist layer is patterned with a grayscale mask that creates a photoresist layer having a sidewall that forms an angle with the horizontal that is less than or equal to 10 degrees.

公开(公告)号：US10978548B2

公开(公告)日：2021-04-13

申请号：US15348580

申请日：2016-11-10

申请人： Texas Instruments Incorporated

发明人： Elizabeth Costner Stewart ,  Jeffrey A. West ,  Thomas D. Bonifield ,  Joseph Andre Gallegos ,  Jay Sung Chun ,  Zhiyi Yu

IPC分类号： H01L49/02 ,  H01L21/02 ,  H01L21/311

摘要： A method of forming an integrated capacitor on a semiconductor surface on a substrate includes etching a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate which is above and electrically isolated from the semiconductor surface to provide at least one defined dielectric feature having sloped dielectric sidewall portion. A dielectric layer is deposited to at least partially fill pits in the sloped dielectric sidewall portion to smooth a surface of the sloped dielectric sidewall portion. The dielectric layer is etched, and a top plate is then formed on top of the dielectric feature.

公开(公告)号：US20190198604A1

公开(公告)日：2019-06-27

申请号：US15850999

申请日：2017-12-21

申请人： Texas Instruments Incorporated

发明人： Elizabeth C. Stewart ,  Jeffrey Alan West ,  Thomas D. Bonifield ,  Jay Sung Chun ,  Byron Lovell Williams

IPC分类号： H01L49/02 ,  H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L23/522

CPC分类号： H01L28/40 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L23/5223

摘要： Methods of fabricating a thick oxide feature on a semiconductor wafer include forming a oxide layer having a thickness of at least six micrometers and depositing a photoresist layer on the oxide layer. The oxide layer has a first etch rate of X with a given etchant, the photoresist layer has a second etch rate of Y with the given etchant and the ratio of X:Y is less than 4:1. Prior to etching the photoresist layer and the oxide layer, the photoresist layer is patterned with a grayscale mask that creates a photoresist layer having a sidewall that forms an angle with the horizontal that is less than or equal to 10 degrees.

公开(公告)号：US20150333055A1

公开(公告)日：2015-11-19

申请号：US14277851

申请日：2014-05-15

申请人： Texas Instruments Incorporated

发明人： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC分类号： H01L27/06 ,  H01L21/02 ,  H01L21/8234 ,  H01L49/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L28/91 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823481 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L29/0692 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/7833

摘要： A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

摘要翻译： 微电子器件包含具有高电压节点和低电压节点的高电压分量。 高电压节点通过微电子器件的基板的表面处的高压节点和低电压元件之间的主电介质与低电压节点隔离。 低压隙电介质层设置在高电压节点和主电介质之间。 低带隙电介质层含有至少一个带隙能量小于主电介质带隙能量的子层。 低带隙电介质层围绕高压节点连续延伸超过高压节点。 较低带隙电介质层具有围绕高电压节点的隔离断裂，距离高压节点的至少两倍于低带隙电介质层的厚度。

公开(公告)号：US11869933B2

公开(公告)日：2024-01-09

申请号：US17398292

申请日：2021-08-10

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Raja Selvaraj ,  Anant Shankar Kamath ,  Byron Lovell Williams ,  Thomas D. Bonifield ,  John Kenneth Arch

IPC分类号： H01L29/06 ,  H01L27/06 ,  H01L21/761 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02 ,  H01L21/265

CPC分类号： H01L29/0646 ,  H01L21/265 ,  H01L21/761 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5286 ,  H01L24/05 ,  H01L27/0676 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/48463

摘要： Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.