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公开(公告)号：US11809206B2
公开(公告)日：2023-11-07
申请号：US17446132
申请日：2021-08-26
Applicant: Texas Instruments Incorporated
CPC classification number: G05F1/56 , H03F1/0216 , H04B1/16 , H03F2200/102 , H03F2200/165
Abstract: An example apparatus includes: a compensation circuit including: a current compensation output, a first transistor with a first current terminal and a first control terminal, the first current terminal coupled to the current compensation output, and a resistor ladder with a tap terminal coupled to the first control terminal, a current mirror circuit having a mirror input and a mirror output, the mirror input coupled to the current compensation output, and a rectification circuit having an input coupled to the mirror output.
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公开(公告)号：US11792051B2
公开(公告)日：2023-10-17
申请号：US17352663
申请日：2021-06-21
Applicant: Texas Instruments Incorporated
Inventor： Sadia Arefin Khan , Anant Shankar Kamath , Martin Staebler , Vikas Kumar Thawani
IPC: H04L25/02 , H02K11/33 , H03K19/0175 , H03K19/003 , H02P27/08
CPC classification number: H04L25/0266 , H02K11/33 , H02P27/08 , H03K19/00323 , H03K19/017509 , H03K19/017545
Abstract: A multi-channel digital isolator includes a digital isolator and an interlock circuit. The isolator includes a transmitter having a transmitter output, a receiver having a receiver input and a receiver output, an isolation barrier coupled between the transmitter output and the receiver input, and an output buffer having a buffer input and configured to output an isolated signal. The transmitter is configured to transmit an input signal across the isolation barrier. The interlock circuit has an interlock input coupled to the receiver output and an interlock output coupled to the buffer input. The interlock module is configured to prevent overlapping active states between the first isolated signal and a complementary isolated signal. In some implementations, the digital isolator also includes a dead-time insertion circuit.
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公开(公告)号：US20230155628A1
公开(公告)日：2023-05-18
申请号：US18100131
申请日：2023-01-23
Applicant: Texas Instruments Incorporated
Inventor： Srijan Rastogi , Mayank Garg , Anant Shankar Kamath
CPC classification number: H04B3/36 , H03F3/45179
Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.
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公开(公告)号：US11621711B2
公开(公告)日：2023-04-04
申请号：US17374319
申请日：2021-07-13
Applicant: Texas Instruments Incorporated
Inventor： Anant Shankar Kamath , Kanteti Amar , Bharath Kumar Singareddy , Rakesh Hariharan
IPC: H03K19/00
Abstract: Methods, apparatus, systems, and articles of manufacture corresponding to a low area and high speed termination detection circuit with voltage clamping are disclosed. An example apparatus includes a transistor including a first control terminal, first current terminal and a second current terminal, the second current terminal adapted to be coupled to a load. The apparatus further includes a logic gate including an input coupled to the first current terminal. The apparatus further includes a current source including a second control terminal, a third current terminal coupled to a voltage rail and a fourth current terminal coupled to the first current terminal and the input of the logic gate.
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公开(公告)号：US20230025757A1
公开(公告)日：2023-01-26
申请号：US17489483
申请日：2021-09-29
Applicant: Texas Instruments Incorporated
Inventor： RR Manikandan , Kumar Anurag Shrivastava , Robert Floyd Payne , Anant Shankar Kamath , Swaminathan Sankaran , Kishalay Datta , Siraj Akhtar , Mark Edward Wentroble , Suvadip Banerjee , Rakesh Hariharan , Gurumurti Kailaschandra Avhad
Abstract: In described examples, an integrated circuit includes an on-off keying (OOK) digital isolator, which includes a first circuitry, a multiplexer, an OOK modulator, an isolation barrier, an OOK envelope detector, and a second circuitry. The first circuitry generates and outputs a calibration signal. The multiplexer has a data signal input, and an input coupled to a first circuitry output. An OOK modulator input is coupled to a multiplexer output. An isolation barrier input is coupled to an OOK modulator output. An OOK envelope detector input is coupled to an isolation barrier output. The second circuitry includes an input coupled to an OOK envelope detector output, and an output coupled to an OOK envelope detector control input. The second circuitry detects a duty cycle distortion (DCD) of the OOK envelope detector output, and outputs a control signal to change the OOK envelope detector output's duty cycle based on the detected DCD.
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Patent Agency Ranking
公开(公告)号：US20220350766A1
公开(公告)日：2022-11-03
申请号：US17246137
申请日：2021-04-30
Applicant: Texas Instruments Incorporated
Inventor： Anant Shankar Kamath , Rakesh Hariharan , Mark Edward Wentroble
Abstract: An isolating repeater and corresponding method for Universal Serial Bus (USB) communications. The isolating repeater includes, on either side of a galvanic isolation barrier, front end circuitry coupled to a pair of external terminals, a full speed (FS) transceiver adapted to drive and receive signals over one or more FS isolation channels, and a high speed (HS) transceiver adapted to drive signals over a one HS isolation channel and receive signals over another HS isolation channel. The front end circuitry encodes received signals corresponding to HS data into two-state signals for transmission over one HS isolation channel, and encodes received signals corresponding to HS signaling into two-state signals for transmission over one or more of the FS isolation channels. The front end circuitry on the other side of the isolation barrier decodes the two-state signals received over the one or more FS isolation channels and the two-state signals received over the HS isolation channel for transmission at its external terminals.
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公开(公告)号：US20210367030A1
公开(公告)日：2021-11-25
申请号：US17398292
申请日：2021-08-10
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Raja Selvaraj , Anant Shankar Kamath , Byron Lovell Williams , Thomas D. Bonifield , John Kenneth Arch
IPC: H01L29/06 , H01L27/06 , H01L49/02 , H01L21/761 , H01L21/265 , H01L23/522 , H01L23/528 , H01L23/00
Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.
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公开(公告)号：US11107883B2
公开(公告)日：2021-08-31
申请号：US16228817
申请日：2018-12-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Raja Selvaraj , Anant Shankar Kamath , Byron Lovell Williams , Thomas D. Bonifield , John Kenneth Arch
IPC: H01L27/06 , H01L23/522 , H01L23/528 , H01L23/00 , H01L29/06 , H01L49/02 , H01L21/761 , H01L21/265
Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.
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公开(公告)号：US20200280262A1
公开(公告)日：2020-09-03
申请号：US16804352
申请日：2020-02-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Anant Shankar Kamath
Abstract: In accordance with an example embodiment, an isolation circuit for electrically isolating a first circuit operating at a first voltage from a second circuit operating at a second voltage that is different than the first voltage is provided. The isolation circuit comprises: a first voltage source that operates at the first voltage, the first voltage source having a first supply rail and a second supply rail; an isolation device having a first input, a second input, a first output and a second output, the second input coupled to a first ground potential and the second output coupled to a second ground potential that is electrically isolated from the first ground potential by the isolation device; a first resistor coupled between the first supply rail and the first input of the isolation device; a second resistor coupled to the first input of the isolation device and the second input of the isolation device; and wherein the first output of the isolation device is coupled to the second circuit.
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公开(公告)号：US20190148486A1
公开(公告)日：2019-05-16
申请号：US16228817
申请日：2018-12-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Raja Selvaraj , Anant Shankar Kamath , Byron Lovell Williams , Thomas D. Bonifield , John Kenneth Arch
IPC: H01L29/06 , H01L49/02 , H01L23/528 , H01L23/522 , H01L23/00 , H01L21/761 , H01L27/06 , H01L21/265
Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.
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