A memory access apparatus includes a read-write module and a processing module. The read-write module is configured to store an error detecting code in an (M+2)th DRAM in the memory row, and store the error correcting code in a Zth DRAM in the memory row, where Z is a positive integer, 1≦Z≦(M+1), and error correcting codes in consecutive (M+1) memory rows are stored in different DRAMs. The processing module is configured to calculate one group of error detecting code for each single chip burst cluster (SCBC) in a memory row, and calculate one group of error correcting code for all SCBCs in a memory row.