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公开(公告)号：US20160154687A1
公开(公告)日：2016-06-02
申请号：US15015303
申请日：2016-02-04
Applicant: Huawei Technologies Co., Ltd.
Inventor： Shuchang Shan , Bing Li , Yu Hu , Xiang Gao
CPC classification number: G06F11/008 , G06F11/1004
Abstract: A hierarchical and flexible method for setting a memory reliability level to implement a memory access mechanism for different running object types and different reliability levels. The method implemented by the memory device includes receiving reliability level information of a running object of a processor sent by the processor; establishing a mapping relationship according to the reliability level information of the running object; receiving an access request sent by the processor; and accessing data of the running object and error-tolerant code of the running object according to the access request and the mapping relationship.
Abstract translation: 一种用于设置内存可靠性级别以实现不同运行对象类型和不同可靠性级别的内存访问机制的分层和灵活方法。 由该存储装置实现的方法包括接收由处理器发送的处理器的运行对象的可靠性级别信息; 根据运行对象的可靠性级别信息建立映射关系; 接收处理器发送的访问请求; 并根据访问请求和映射关系访问正在运行的对象的数据和运行对象的容错代码。
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Patent Agency Ranking
公开(公告)号：US09811416B2
公开(公告)日：2017-11-07
申请号：US15010326
申请日：2016-01-29
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Xiang Gao , Bing Li , Shuchang Shan , Yu Hu
CPC classification number: G06F11/1068 , G06F11/1044 , G06F11/108 , G11C29/52
Abstract: A memory access apparatus includes a read-write module and a processing module. The read-write module is configured to store an error detecting code in an (M+2)th DRAM in the memory row, and store the error correcting code in a Zth DRAM in the memory row, where Z is a positive integer, 1≦Z≦(M+1), and error correcting codes in consecutive (M+1) memory rows are stored in different DRAMs. The processing module is configured to calculate one group of error detecting code for each single chip burst cluster (SCBC) in a memory row, and calculate one group of error correcting code for all SCBCs in a memory row.
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公开(公告)号：US10069604B2
公开(公告)日：2018-09-04
申请号：US15096393
申请日：2016-04-12
Applicant: Huawei Technologies Co., Ltd.
Inventor： Xing Hu , Yu Hu , Shuchang Shan , Xiaowei Li
IPC: H04L1/22 , H04L12/801 , H04L12/709 , H04L29/08 , H04L29/12 , H04L12/703 , H04L1/00
Abstract: A data transmission method and apparatus, where the method comprises checking full-bandwidth transmission paths of a bus, and When a fault occurs in the full-bandwidth transmission paths and a quantity of faulty full-bandwidth transmission paths is less than or equal to M, selecting N full-bandwidth transmission paths from full-bandwidth transmission paths that are not faulty to transmit a data unit, and when a fault occurs in the full-bandwidth transmission paths and a quantity of faulty full-bandwidth transmission paths is greater than M, reconfiguring a size of a data unit according to a quantity of full-bandwidth transmission paths that are not faulty and a target burst quantity.
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公开(公告)号：US20160147600A1
公开(公告)日：2016-05-26
申请号：US15010326
申请日：2016-01-29
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Xiang Gao , Bing Li , Shuchang Shan , Yu Hu
CPC classification number: G06F11/1068 , G06F11/1044 , G06F11/108 , G11C29/52
Abstract: A memory access apparatus includes a read-write module and a processing module. The read-write module is configured to store an error detecting code in an (M+2)th DRAM in the memory row, and store the error correcting code in a Zth DRAM in the memory row, where Z is a positive integer, 1≦Z≦(M+1), and error correcting codes in consecutive (M+1) memory rows are stored in different DRAMs. The processing module is configured to calculate one group of error detecting code for each SCBC in a memory row, and calculate one group of error correcting code for all SCBCs in a memory row.
Abstract translation: 存储器访问装置包括读写模块和处理模块。 读写模块被配置为在存储行中的第（M + 2）DRAM中存储错误检测码，并将纠错码存储在存储行中的第Z个DRAM中，其中Z是正整数1＆nlE （M + 1）和连续（M + 1）个存储器行中的纠错码存储在不同的DRAM中。 处理模块被配置为对存储器行中的每个SCBC计算一组检错码，并计算存储器行中所有SCBC的一组纠错码。
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公开(公告)号：US09772891B2
公开(公告)日：2017-09-26
申请号：US15015303
申请日：2016-02-04
Applicant: Huawei Technologies Co., Ltd.
Inventor： Shuchang Shan , Bing Li , Yu Hu , Xiang Gao
CPC classification number: G06F11/008 , G06F11/1004
Abstract: A hierarchical and flexible method for setting a memory reliability level to implement a memory access mechanism for different running object types and different reliability levels. The method implemented by the memory device includes receiving reliability level information of a running object of a processor sent by the processor; establishing a mapping relationship according to the reliability level information of the running object; receiving an access request sent by the processor; and accessing data of the running object and error-tolerant code of the running object according to the access request and the mapping relationship.
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公开(公告)号：US20160226633A1
公开(公告)日：2016-08-04
申请号：US15096393
申请日：2016-04-12
Applicant: Huawei Technologies Co., Ltd.
Inventor： Xing Hu , Yu Hu , Shuchang Shan , Xiaowei Li
CPC classification number: H04L1/22 , H04L1/0007 , H04L29/12575 , H04L45/245 , H04L45/28 , H04L47/10 , H04L69/324 , H04L69/326 , H04L2001/0094
Abstract: A data transmission method and apparatus, where the method comprises checking full-bandwidth transmission paths of a bus, and When a fault occurs in the full-bandwidth transmission paths and a quantity of faulty full-bandwidth transmission paths is less than or equal to M, selecting N full-bandwidth transmission paths from full-bandwidth transmission paths that are not faulty to transmit a data unit, and when a fault occurs in the full-bandwidth transmission paths and a quantity of faulty full-bandwidth transmission paths is greater than M, reconfiguring a size of a data unit according to a quantity of full-bandwidth transmission paths that are not faulty and a target burst quantity.
Abstract translation: 一种数据传输方法和装置，其中该方法包括检查总线的全带宽传输路径，当在全带宽传输路径中出现故障时，一批有缺陷的全带宽传输路径小于或等于M 从全带宽传输路径中选择N个全带宽传输路径，这些传输路径不发送数据单元，当全带宽传输路径发生故障时，一批故障全带宽传输路径大于M 根据不具有故障的全带宽传输路径的数量和目标突发量重新配置数据单元的大小。
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