- 专利标题： Memory system with timing overlap mode for activate and precharge operations
-
申请号： US15370114申请日： 2016-12-06
-
公开(公告)号： US09870812B2公开(公告)日： 2018-01-16
- 发明人: Thomas Andre , Syed M. Alam , Halbert S. Lin
- 申请人： Everspin Technologies, Inc.
- 申请人地址： US AZ Chandler
- 专利权人： EVERSPIN TECHNOLOGIES, INC.
- 当前专利权人： EVERSPIN TECHNOLOGIES, INC.
- 当前专利权人地址： US AZ Chandler
- 代理机构： Bookoff McAndrews, PLLC
- 主分类号： G11C7/00
- IPC分类号： G11C7/00 ; G11C11/16 ; G11C7/12 ; G11C7/10 ; G11C7/22 ; G06F12/0802 ; G11C11/4076
摘要：
In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.
公开/授权文献
- US20170084324A1 MEMORY DEVICE WITH TIMING OVERLAP MODE 公开/授权日：2017-03-23
信息查询
