- 专利标题： Semiconductor integrated circuit adapted to output pass/fail results of internal operations
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申请号： US15363808申请日： 2016-11-29
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公开(公告)号： US09870831B2公开(公告)日： 2018-01-16
- 发明人: Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
- 申请人： TOSHIBA MEMORY CORPORATION
- 申请人地址： JP Minato-ku
- 专利权人： TOSHIBA MEMORY CORPORATION
- 当前专利权人： TOSHIBA MEMORY CORPORATION
- 当前专利权人地址： JP Minato-ku
- 代理机构： Oblon, McClelland, Maier & Neustadt, L.L.P.
- 优先权： JP2001-386596 20011219; JP2002-311475 20021025
- 主分类号： G11C7/00
- IPC分类号： G11C7/00 ; G11C16/34 ; G11C7/06 ; G11C7/10 ; G11C16/10 ; G11C16/26 ; G06F3/06 ; G06F12/02 ; G11C16/06 ; G11C16/08
摘要：
In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
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