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公开(公告)号：US20220139471A1
公开(公告)日：2022-05-05
申请号：US17578956
申请日：2022-01-19
发明人： Noboru SHIBATA , Tomoharu TANAKA
摘要： Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining l0 the first memory cells in the bit line direction.
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公开(公告)号：US20220100377A1
公开(公告)日：2022-03-31
申请号：US17643034
申请日：2021-12-07
发明人： Hiroshi YAO , Shinichi KANNO , Kazuhiro FUKUTOMI
摘要： According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.
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3.发明申请公开(公告)号：US20220083497A1
公开(公告)日：2022-03-17
申请号：US17537126
申请日：2021-11-29
发明人： Yaron KLEIN
IPC分类号： G06F15/173 , G06F3/06 , G06F12/02 , H04L29/06
摘要： A system for reading stored data may include one or more Ethernet drives and a controller, both configured to communicatively connect to a host device. The controller may receive a first read command from the host device, determine a first drive among the one or more Ethernet drives using the first read command and a mapping table, translate the first read command into a second read command, and send the second read command to the first drive. Responsive to receiving the second read command, the first drive may send a first remote data transfer instruction to the host device independent of the controller. The first remote data transfer instruction may include stored data read from the first drive to cause the host device to write the stored data read from the first drive to one or more memory buffers in the host device indicated by the second read command.
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4.发明申请公开(公告)号：US20220083278A1
公开(公告)日：2022-03-17
申请号：US17536502
申请日：2021-11-29
发明人： Shinichi KANNO
摘要： According to one embodiment, a storage system performs a first allocation operation of allocating, for a first namespace, a plurality of first blocks included in the blocks of a nonvolatile memory. The storage system performs a read operation, a write operation or an erase operation on one of the first blocks in response to a command received from a host to read, write or erase the one first block, counts the total number of erase operations performed on the first blocks, and notifies the host of the counted number of erase operations in response to a command received from the host to obtain an erase count associated with the first namespace.
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公开(公告)号：US20220077170A1
公开(公告)日：2022-03-10
申请号：US17524984
申请日：2021-11-12
发明人： Yoshiaki FUKUZUMI , Keisuke SUDA , Fumiki AISO , Atsushi FUKUMOTO
IPC分类号： H01L27/11556 , H01L27/11582 , G11C16/04 , G11C5/06
摘要： A semiconductor memory includes a substrate, a source line layer above the substrate in a memory region and a peripheral region of the substrate, a first insulating layer above the source line layer, a first conductive layer on the first insulating layer in the memory and peripheral regions, an alternating stack of a plurality of second insulating layers and a plurality of second conductive layers on the first conductive layer in the memory region, and a plurality of pillars extending through the alternating stack of the second insulating layers and the second conductive layers, the first conductive layer, and the first insulating layer in the memory region. A bottom end of each of the pillars is in the source line layer in a thickness direction. A carrier density of the source line layer is higher in the memory region than in the peripheral region.
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6.发明授权公开(公告)号：US11257551B2
公开(公告)日：2022-02-22
申请号：US17168822
申请日：2021-02-05
发明人： Akio Sugahara , Takaya Handa , Ryosuke Isomura , Kazuto Uehara , Junichi Sato , Norichika Asaoka , Masashi Yamaoka , Bushnaq Sanad , Yuzuru Shibazaki , Noriyasu Kumazaki , Yuri Terada
摘要： A method of controlling a memory device includes receiving an address indicating a region in a memory cell array and generating one or more voltages supplied to the memory cell array in parallel with receiving the address.
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公开(公告)号：US11251193B2
公开(公告)日：2022-02-15
申请号：US16558725
申请日：2019-09-03
发明人： Ken Komiya , Takashi Ishida , Hiroshi Kanno
IPC分类号： H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L21/74 , H01L29/10 , H01L27/1157
摘要： A semiconductor memory device includes a substrate, gate electrodes arranged in a thickness direction of the substrate, first and second semiconductor layers, a gate insulating film, and a first contact. The first semiconductor layer extends in the thickness direction and faces the gate electrodes. The gate insulating film is between the gate electrodes and the first semiconductor layer. The second semiconductor layer is between the substrate and the gate electrodes and connected to a side surface of the first semiconductor layer in a surface direction. The first contact extends in the thickness direction and electrically connected to the second semiconductor layer. The second semiconductor layer includes a first region in contact with the side surface of the first semiconductor layer and containing P-type impurities, and a first contact region electrically connected to the first contact and having a higher concentration of N-type impurities than the first region.
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公开(公告)号：US11237756B2
公开(公告)日：2022-02-01
申请号：US16803106
申请日：2020-02-27
发明人： Shinichi Kanno , Hideki Yoshida , Naoki Esaka
IPC分类号： G06F3/06 , G06F12/0804
摘要： According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writing the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.
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公开(公告)号：US11222144B2
公开(公告)日：2022-01-11
申请号：US16286520
申请日：2019-02-26
发明人： Takaya Ogawa
IPC分类号： G06F21/78 , G06F3/06 , G06F1/3228 , H04L9/08
摘要： A storage device includes a controller configured to control the storage device, and a storage area for security information, the security information including flag information indicating whether reading or writing of data from/to the storage device is permitted and time information indicating a cumulative time value during which power of the storage device has been turned on. When a first command is received from a host device, the controller generates encrypted data by encrypting data obtained by combining the time information and the security information, and after transmitting the encrypted data to the host device, shifts the storage device to a low power state.
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公开(公告)号：US11211541B2
公开(公告)日：2021-12-28
申请号：US16459777
申请日：2019-07-02
发明人： Takeshi Yamane
摘要： According to one embodiment, a superconducting element used as a pixel for detecting a particle is disclosed. The superconducting element includes at least one superconducting strip. The at least one superconducting strip includes a superconducting portion extending in a first direction, including first and second ends and made of a first superconducting material, a first conductive portion connected to the first end of the superconducting portion, and a second conductive portion connected to the second end of the superconducting portion. A superconducting region of the superconducting portion is configured to be dived when the particle is made incident on the superconducting portion along the first direction via the first conductive portion.
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