公开(公告)号：US10741266B2

公开(公告)日：2020-08-11

申请号：US16534359

申请日：2019-08-07

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hiroshi Nakamura ,  Kenichi Imamiya ,  Toshio Yamamura ,  Koji Hosono ,  Koichi Kawai

IPC: G11C7/00 ,  G11C16/34 ,  G11C7/06 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26 ,  G06F3/06 ,  G06F12/02 ,  G11C16/06 ,  G11C16/08

Abstract: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

公开(公告)号：US10410731B2

公开(公告)日：2019-09-10

申请号：US15831805

申请日：2017-12-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hiroshi Nakamura ,  Kenichi Imamiya ,  Toshio Yamamura ,  Koji Hosono ,  Koichi Kawai

IPC: G11C7/00 ,  G11C16/34 ,  G11C7/06 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26 ,  G06F3/06 ,  G06F12/02 ,  G11C16/06 ,  G11C16/08

Abstract: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

公开(公告)号：US10658039B2

公开(公告)日：2020-05-19

申请号：US16149862

申请日：2018-10-02

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Makoto Iwai ,  Hiroshi Nakamura

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  G11C16/26 ,  G11C16/06 ,  G11C16/08

Abstract: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

公开(公告)号：US10074434B2

公开(公告)日：2018-09-11

申请号：US15791178

申请日：2017-10-23

Applicant: Toshiba Memory Corporation

Inventor： Masanobu Shirakawa ,  Takuya Futatsuyama ,  Kenichi Abe ,  Hiroshi Nakamura ,  Keisuke Yonehama ,  Atsuhiro Sato ,  Hiroshi Shinohara ,  Yasuyuki Baba ,  Toshifumi Minami

IPC: G11C16/04 ,  G11C16/14 ,  G11C11/56 ,  G11C29/42 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L27/1157 ,  G11C16/34

CPC classification number: G11C16/14 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3445 ,  G11C29/42 ,  H01L27/1157 ,  H01L27/11582

Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

公开(公告)号：US11087845B2

公开(公告)日：2021-08-10

申请号：US16844258

申请日：2020-04-09

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Makoto Iwai ,  Hiroshi Nakamura

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  G11C16/26 ,  G11C16/06 ,  G11C16/08

Abstract: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

公开(公告)号：US20200234767A1

公开(公告)日：2020-07-23

申请号：US16844258

申请日：2020-04-09

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Makoto Iwai ,  Hiroshi Nakamura

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  G11C16/26 ,  G11C16/06 ,  G11C16/08

Abstract: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

公开(公告)号：US20180096729A1

公开(公告)日：2018-04-05

申请号：US15831805

申请日：2017-12-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hiroshi Nakamura ,  Kenichi Imamiya ,  Toshio Yamamura ,  Koji Hosono ,  Koichi Kawai

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/06 ,  G06F12/02 ,  G06F3/06 ,  G11C7/06 ,  G11C16/26 ,  G11C16/10 ,  G11C7/10

CPC classification number: G11C16/3459 ,  G06F3/0659 ,  G06F12/0246 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1063 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2207/104 ,  G11C2216/14

Abstract: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

公开(公告)号：US10854298B2

公开(公告)日：2020-12-01

申请号：US16459495

申请日：2019-07-01

Applicant: Toshiba Memory Corporation

Inventor： Masanobu Shirakawa ,  Takuya Futatsuyama ,  Kenichi Abe ,  Hiroshi Nakamura ,  Keisuke Yonehama ,  Atsuhiro Sato ,  Hiroshi Shinohara ,  Yasuyuki Baba ,  Toshifumi Minami

IPC: G11C16/04 ,  G11C16/14 ,  H01L27/1157 ,  H01L27/11582 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42 ,  G11C16/34

Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

公开(公告)号：US10381084B2

公开(公告)日：2019-08-13

申请号：US16056835

申请日：2018-08-07

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Masanobu Shirakawa ,  Takuya Futatsuyama ,  Kenichi Abe ,  Hiroshi Nakamura ,  Keisuke Yonehama ,  Atsuhiro Sato ,  Hiroshi Shinohara ,  Yasuyuki Baba ,  Toshifumi Minami

IPC: G11C16/04 ,  G11C16/14 ,  H01L27/1157 ,  H01L27/11582 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42 ,  G11C16/34

Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

公开(公告)号：US10109359B2

公开(公告)日：2018-10-23

申请号：US15337592

申请日：2016-10-28

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Makoto Iwai ,  Hiroshi Nakamura

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  G11C16/06 ,  G11C16/08

Abstract: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.