Invention Grant
- Patent Title: Flipped die stack assemblies with leadframe interconnects
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Application No.: US15209034Application Date: 2016-07-13
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Publication No.: US09871019B2Publication Date: 2018-01-16
- Inventor: Ashok S. Prabhu , Rajesh Katkar , Liang Wang , Cyprian Emeka Uzoh
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/495 ; H01L23/00 ; H01L23/31

Abstract:
A microelectronic assembly includes a stack of microelectronic elements, e.g., semiconductor chips, each having a front surface defining a respective plane of a plurality of planes. A leadframe interconnect joined to a contact at a front surface of each chip may extend to a position beyond the edge surface of the respective microelectronic element. The chip stack is mounted to support element at an angle such that edge surfaces of the chips face a major surface of the support element that defines a second plane that is transverse to, i.e., not parallel to the plurality of parallel planes. The leadframe interconnects are electrically coupled at ends thereof to corresponding contacts at a surface of the support element.
Public/Granted literature
- US20170018485A1 FLIPPED DIE STACK ASSEMBLIES WITH LEADFRAME INTERCONNECTS Public/Granted day:2017-01-19
Information query
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