Invention Grant
- Patent Title: Method for local isolation between transistors produced on an SOI substrate, in particular an FDSOI substrate, and corresponding integrated circuit
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Application No.: US14956594Application Date: 2015-12-02
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Publication No.: US09876076B2Publication Date: 2018-01-23
- Inventor: Emmanuel Perrin
- Applicant: STMICROELECTRONICS (CROLLES 2) SAS
- Applicant Address: FR Crolles
- Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee Address: FR Crolles
- Agency: Seed IP Law Group LLP
- Priority: FR1554853 20150529
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/66 ; H01L21/84 ; H01L27/12 ; H01L21/8238 ; H01L21/762

Abstract:
An integrated circuit may include an SOI substrate having a buried insulating layer, and a semiconductor film above the buried insulating layer. The semiconductor film may have first patterns in a first zone defining gate regions of first MOS transistors and also first dummy gate regions. The first zone may include two domains having a space therebetween, and the space may be filled by at least one insulating material and be situated between two dummy gate regions above a region of the supporting substrate without any insulating trench.
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